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Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Editor-in-Chief Harry Levinson introduces a new set of guidelines for papers related to computational lithography.

“Writing on dirty paper” refers to the communication problem over a channel with both noise and interference, where the interference is known to the encoder non-causally and unknown to the decoder. This problem is regarded as a basic building block in both the single-user and multiuser communications, and it has been extensively investigated by Costa and other researchers. However, little is known in the case that the encoder can have access to feedback from the decoder. In this paper, we study the dirty-paper coding problem for feedback Gaussian channels without or with memory. We provide the most power efficient coding schemes for this problem, i.e., the schemes achieve lossless interference cancelation. These schemes are based on the Kalman filtering algorithm, extend the Schalkwijk-Kailath feedback codes, have low complexity and a doubly exponential reliability function, and reveal the interconnections among information, control, and estimation over dirty-paper channels with feedback. This research may be found useful to, for example, powerconstrained sensor network communication.

We develop a system for generating embedded diagnostics from an ODE model that can isolate faults given the memory and processing limitations of the embedded processor. This system trades off diagnosis isolation accuracy for inference time and/or memory in a principled manner. We use a Polynomial Regression approach for tuning the performance of an ensemble of low-fidelity ODE diagnosis models such that we achieve the target of embedded processing limits. We demonstrate our approach on a non-linear tank benchmark system.

This paper describes the problem of intelligent paper grouping and its mathematical model. By optimizing and improving the traditional dynamic programming algorithm, its space complexity is reduced from O(nb) to O(b). At the same time, the flexibility of dynamic programming algorithm is increased by using marker function and tracking algorithm, and the result composition is tracked to obtain the optimal solution. Finally, through several experiments, the improved dynamic programming algorithm is compared with the greedy algorithm and brute force algorithm, and it is found that the improved dynamic programming algorithm has a very good result and is with high efficiency when applied to the simple test paper. It is the most recommended algorithm among the two algorithms compared in this paper.

Recently, EM lens-embedded massive array antennas have been proposed for next 5G mobile wireless communications, as the adoption of a lens allows to discriminate the AOA of signals in the analog domain, with the possibility to preserve the processing complexity lower with respect to traditional massive arrays. In fact, in such a way, complex ADC chains can be avoided and the number of required antennas can be decreased. By exploiting these advantages, in this paper we study the possibility to use a single EM lens massive array at mm-wave for the AOA estimation of the received signal. In this perspective, ML estimator and practical approaches, tailored for the considered scenario, are derived. Results, obtained for different number of antennas, confirm the possibility to achieve interesting AOA estimation performance with an extremely compact architecture.

Automated techniques for analysis and optimization of finite-precision computations have recently garnered significant interest. Most of these were, however, developed independently. As a consequence, reuse and combination of the techniques is challenging and much of the underlying building blocks have been re-implemented several times, including in our own tools. This paper presents a new framework, called Daisy, which provides in a single tool the main building blocks for accuracy analysis of floating-point and fixed-point computations which have emerged from recent related work. Together with its modular structure and optimization methods, Daisy allows developers to easily recombine, explore and develop new techniques. Daisy’s input language, a subset of Scala, and its limited dependencies make it furthermore user-friendly and portable.

The ever-escalating attacks on the internet network are due to rapid technological growth. In order to surmount such challenges, multi-layer security algorithms were developed by hybridizing cryptography and steganography techniques. Consequently, the overall memory size became enormous while hybridizing these techniques. On the other side, the least significant bit (LSB) and modified LSB replacing approaches could provide the variability as detected by steganalysis technique, most found to be susceptible to attack too due to numerous reasons. To overcome these issues, in this paper a lightweight and optimized data hiding algorithm is proposed which consume less memory, provide less variability, and robust against histogram attacks. The proposed steganography system was achieved in two stages. First, data was encrypted using lightweight BORON cipher that only consumed less memory as compared to conventional algorithm such as 3DES, AES. Second, the encrypted data was hidden in the complemented or non-complemented form to obtain minimal variability. The performance of the proposed technique was evaluated in terms of avalanche effect, visual quality, embedding capacity and peak signal to noise ratio (PSNR). The results revealed that the lightweight BORON cipher could produce approximate same avalanche effect as the AES algorithm produced. Furthermore, the value of PSNR had shown much improvement in comparison to optimization algorithm GA.

International audience; This paper deals with the improvement of the Dirty Paper Trellis Code (DPTC) watermarking algorithm. This watermarking algorithm is known to be one of the best among the high rate watermarking schemes. Nevertheless, recent researches reveal its security weakness. Previously, we proposed to reinforce its security by using a secret space before the embedding. This secret space requires to compute projections onto secrets carriers. When dealing with high rate watermarking, the CPU cost for those projections is dramatically high. After introducing the watermarking scheme, we then propose two Space Division Multiplexing (SDM) approaches which reduce the complexity. Evaluations are achieved with four different attacks and show that our proposal gives better robustness results with SDM approaches.

The recent breakthroughs of deep reinforcement learning (DRL) technique in Alpha Go and playing Atari have set a good example in handling large state and actions spaces of complicated control problems. The DRL technique is comprised of (i) an offline deep neural network (DNN) construction phase, which derives the correlation between each state-action pair of the system and its value function, and (ii) an online deep Q-learning phase, which adaptively derives the optimal action and updates value estimates. In this paper, we first present the general DRL framework, which can be widely utilized in many applications with different optimization objectives. This is followed by the introduction of three specific applications: the cloud computing resource allocation problem, the residential smart grid task scheduling problem, and building HVAC system optimal control problem. The effectiveness of the DRL technique in these three cyber-physical applications have been validated. Finally, this paper investigates the stochastic computing-based hardware implementations of the DRL framework, which consumes a significant improvement in area efficiency and power consumption compared with binary-based implementation counterparts.

A knowledge map, which has been recently applied in various fields, is discovering characteristics hidden in a large amount of information and showing a tangible output to understand the meaning of the discovery. In this paper, we suggested a knowledge map for research trend analysis based on keyword-relation networks which are constructed by using a database of the domestic journal articles in the computer engineering field from 2000 through 2010. From that knowledge map, we could infer influential changes of a research topic related a specific keyword through examining the change of sizes of the connected components to which the keyword belongs in the keyword-relation networks. In addition, we observed that the size of the largest connected component in the keyword-relation networks is relatively small and groups of high-similarity keyword pairs are clustered in them by comparison with the random networks. This implies that the research field corresponding to the largest connected component is not so huge and many small-scale topics included in it are highly clustered and loosely-connected to each other. our proposed knowledge map can be considered as a approach for the research trend analysis while it is impossible to obtain those results by conventional approaches such as analyzing the frequency of an individual keyword.

This tutorial paper surveys recent developments in parallel computer architecture, focusing on the field-programmable gate array and the graphics processor. We aim to illustrate the potential of these architectures for the type of high-speed numerical computation required in on-line optimization for model predictive control. While significant performance advantages can be gained by migrating existing control algorithms to these processor architectures, in order to realise their full potential, further research is needed at the boundary of control theory, digital electronics, and computer architecture. We survey some of the open questions in this area.

This paper describes the neural-based recognition and verification techniques used in a banknote machine, recently implemented for accepting paper currency of different countries. The perception mechanism is based on low-cost optoelectronic devices which produce a signal associated with the light refracted by the banknotes. The classification and verification steps are carried out by a society of multilayer perceptrons whose operation is properly scheduled by an external controlling algorithm, which guarantees real-time implementation on a standard microcontroller-based platform. The verification relies mainly on the property of autoassociators to generate closed separation surfaces in the pattern space. The experimental results are very interesting, particularly when considering that the recognition and verification steps are based on low-cost sensors.

Space-time adaptive processing (STAP) and related adaptive array techniques hold tremendous potential for improving sensor performance by exploiting signal diversity. Such methods have important application in radar, sonar, and communication systems. Recent advances in digital signal processing technology now provide the computational means to field STAP-based systems. The objective of this special collection of papers is to examine the current state-of-the art in STAP technology and explore the remaining obstacles, practical issues and novel techniques required to implement STAP-based radar, sonar or communication systems.

A computer program is described that enables a user of the ANL IBM-370/195 computer system to process data punched in standard ASCII code on a paper tape as though they were punched on standard IBM cards.

This paper examines the history of electrical engineering education, leveraging the concept of “expansive (dis)integration” to frame a number of key trends and challenges in the field. Our account is organized historically, starting with the origins and early development of electrical engineering education beginning in the late 1800s, and then tracing out the rise of new subfields and specialties during the inter-war and post-WWII periods. The development of computer engineering as a field is given special attention as a case study in disciplinary (dis)integration, while setting the stage for a discussion of broader trends associated with the rising influence of digital techniques and technologies across electrical engineering. The final sections of this paper report on some contemporary challenges and opportunities that may further transform the field in upcoming years and decades, with particular emphasis on issues of demographic diversity and perceptions of broader relevance and impact. The approach of this paper is largely historical, drawing on a wide variety of primary and secondary source materials. It is expected that this paper will be of interest to anyone who would like to know more about the historical development of electrical engineering education, including in relation to more contemporary currents in the field.

Graphical abstractDisplay Omitted HighlightsMultiple-input multiple-output (MIMO) is suitable technique to ensure high speed data transmission as well as low delay communication networks.In MIMO, dirty paper coding (DPC) is an efficient scheme to support multiple users with optimum sum rate capacity of the system. However, DPC is a complex scheme where the user encoding sequence is important to transmit data to multiple users.An optimal exhaustive search as used in DPC is prohibited due to the extremely large size of the search space in this optimization problem.Evolutionary algorithm (genetic algorithm) can be used as an alternative for this optimization problem to reduce the complexity of the search (scheduling problem). The performance of the genetic algorithm with elitism and adaptive mutation is demonstrated to be near optimal as obtained with an exhaustive search. It has been demonstrated in this paper that GA achieves about 98-99% of system sum rate as obtained with DPC with significant reduction in time and computational complexity.The proposed BGA is able to provide the optimum solution well within the packet duration of modern wireless packet data communications. In conventional single-input single-output (SISO) systems, the capacity is limited as base station can provide service to only one user at any instant. However, multiuser (MU) multiple-input multiple-output (MIMO) systems deliver optimum system capacity by providing service to multiple users (as many as transmit antennas) simultaneously according to dirty paper coding (DPC) scheme. However, DPC is an exhaustive search algorithm (ESA) where the user encoding sequence is important to transmit data to multiple users. Exhaustive search becomes imperative as the search space grows with number of users and number of transmit antennas in the MU MIMO system. This can be treated as an optimization problem of maximizing the achievable system sum-rate. In this paper, it has been demonstrated that combined user and antenna scheduling (CUAS) with binary genetic algorithm (BGA) adopting elitism and adaptive mutation (AM) achieves about 97-99% of system sum-rate obtained by ESA (DPC) with significantly reduced computational and time complexity. It has been shown that BGA is able to find the globally optimum solution for MU MIMO systems well within the time interval of modern wireless packet data communications. However, it is interesting to observe that BGA is able to find a solution to CUAS close to the optimum value quite rapidly. In this paper, it is also shown that BGA with elitism and AM achieves higher throughput than limited feedback scheduling schemes as well.

Metasurfaces provide unprecedented routes to manipulations on electromagnetic waves, which can realize many exotic functionalities. Despite the rapid development of metasurfaces in recent years, the design process of metasurface is still time‐consuming and computational resource‐consuming. Moreover, it is quite complicated for layman users to design metasurfaces as plenty of specialized knowledge is required. In this work, a metasurface design method named REACTIVE is proposed on the basis of deep learning, as deep learning method has shown its natural advantages and superiorities in mining undefined rules automatically in many fields. REACTIVE is capable of calculating metasurface structure directly through a given design target; meanwhile, it also shows the advantage in making the design process automatic, more efficient, less time‐consuming, and less computational resource‐consuming. Besides, it asks for less professional knowledge, so that engineers are required only to pay attention to the design target. Herein, a triple‐band absorber is designed using the REACTIVE method, where a deep learning model computes the metasurface structure automatically through inputting the desired absorption rate. The whole design process is achieved 200 times faster than the conventional one, which convincingly demonstrates the superiority of this design method. REACTIVE is an effective design tool for designers, especially for laymen users and engineers.

Purpose: Skin cancer is the most common tumor in the population. There are different therapeutic modalities. Brachytherapy is one of the techniques used, in which it is necessary to build customized moulds for some patients. Currently, these moulds are made by hand using rudimentary techniques. We present a new procedure based on 3D printing and the analysis of the clinical workflow. Material and methods: Moulds can be made either by hand or by automated 3D printing. For making moulds by hand, a patient’s alginate negative is created and, from that, the gypsum cast and customized moulds are made by hand from the patient’s negative template. The new process is based on 3D printing. The first step is to take a 3D scan of the surface of the patient and then, 3D modelling software is used to obtain an accurate anatomical reconstruction of the treatment area. We present the clinical workflow using 3D scanning and printing technology, comparing its costs with the usual custom handmade mould protocol. Results: The time spent for the new process is 6.25 hours, in contrast to the time spent for the conventional process, which is 9.5 hours. We found a 34% reduction in time required to create a mould for brachytherapy treatment. The labor cost of the conventional process is 211.5 vs. 152.5 hours, so the reduction is 59 hours. There is also a 49.5% reduction in the financial costs, mostly due to lack of need of a computed tomography (CT) scan of the gypsum and the mould. 3D scanning and printing offers financial benefits and reduces the clinical workload. Conclusions : As the present project demonstrates, through the application of 3D printing technologies, the costs and time spent during the process in the clinical workload in brachytherapy treatment are reduced. Overall, 3D printing is a promising technique for brachytherapy that might be well received in the community.

Motivation: Next Generation Sequencing (NGS) technologies have revolutionized genomic research by reducing the cost of whole genome sequencing. One of the biggest challenges posed by modern sequencing technology is economic storage of NGS data. Storing raw data is infeasible because of its enormous size and high redundancy. In this article, we address the problem of storage and transmission of large FASTQ files using innovative compression techniques. Results: We introduce a new lossless non-reference based FASTQ compression algorithm named Lossless FASTQ Compressor. We have compared our algorithm with other state of the art big data compression algorithms namely gzip, bzip2, fastqz (Bonfield and Mahoney, 2013), fqzcomp (Bonfield and Mahoney, 2013), Quip (Jones et al., 2012), DSRC2 (Roguski and Deorowicz, 2014). This comparison reveals that our algorithm achieves better compression ratios on LS454 and SOLiD datasets. Availability and implementation: The implementations are freely available for non-commercial purposes. They can be downloaded from http://engr.uconn.edu/rajasek/lfqc-v1.1.zip. Contact: rajasek@engr.uconn.edu

Introduction: Computer Engineering Students (CES) and Medical Students (MS) will actively participate in the management of health information system in the future. Aim: The aim of the study was to evaluate the views of CES and MS about the patient privacy and security of health information systems. Methods: The participants of this cross-sectional study were the 3rd and 4th year CES of Marmara University, (n=163, F/M:71/92) and the 5th and 6th year MS of Marmara University (n=65, F/M:38/27). The data were collected via questionnaire comprising questions and statements about patient information security and confidentiality. Responses were prepared on the basis of 5 Point Likert Scale. Results: During the assessment of the questionnaires, it was observed that the statement “Health records should be accessible to the other health workers besides the physician” discomforted more CES (93,3%) than MS (78,5%) (p=0.003). A similar proportion was observed about “On-line communication with the physician” more CES (87,1%) prefer to communicate with the physician via electronic media than do the MS (66,2%) (p=0.001). Another significant point to be noted about the questionnaire results was that slightly more CES (40,5%) favor restrictions on the accessibility of “personal correspondance information” than MS (35,4%) (p>0.05). Conclusion: In the future, CES, who will be both internal and external stakeholders of the multi-disciplinary structure of healthcare management, thought that problems regarding security and privacy may occur. Therefore, the relation between health information system and the occupational education and training of CES and MS are extremely important through the perspective in healthcare management. © 2019 Esra Sevimli, Elif Naz Altingoz, Nur Şisman Kitapci, Okan Cem Kitapci, Leyla Koksal, Meral Yay, Pınar Kilic Aksu, Gonca Mumcu

Conventionally, multi-channel acoustic echo cancellation (AEC) achieves the goal by estimating the impulse responses of the local room. However, generally, conventional AEC methods have no unique solutions. Due to the strong correlation of the input signals, conventional methods are with many disadvantages. To overcome this problems, a new framework is proposed in this paper based on SIMO (single input multiple output) blind deconvolution. Under the new framework, we achieve the goal by identifying the impulse responses of distant room and avoiding the disadvantages of the conventional methods. *Supported by National Natural Science foundation of China (Grand Nos. 60325310, 60505005), Guangdong Province Science Foundation for Program of Research Team (Grant No. 04205783), Guangdong Province Natural Science Foundation (Grant Nos. 05103553,05006508) and the Specialized Prophasic Basic Research Projects of Ministry of science and Technology, china (Grant No. 2005CCA04100)

Motivation: The explosive growth of next-generation sequencing datasets poses a challenge to the mapping of reads to reference genomes in terms of alignment quality and execution speed. With the continuing progress of high-throughput sequencing technologies, read length is constantly increasing and many existing aligners are becoming inefficient as generated reads grow larger. Results: We present CUSHAW2, a parallelized, accurate, and memory-efficient long read aligner. Our aligner is based on the seed-and-extend approach and uses maximal exact matches as seeds to find gapped alignments. We have evaluated and compared CUSHAW2 to the three other long read aligners BWA-SW, Bowtie2 and GASSST, by aligning simulated and real datasets to the human genome. The performance evaluation shows that CUSHAW2 is consistently among the highest-ranked aligners in terms of alignment quality for both single-end and paired-end alignment, while demonstrating highly competitive speed. Furthermore, our aligner shows good parallel scalability with respect to the number of CPU threads. Availability: CUSHAW2, written in C++, and all simulated datasets are available at http://cushaw2.sourceforge.net Contact: liuy@uni-mainz.de; bertil.schmidt@uni-mainz.de Supplementary information: Supplementary data are available at Bioinformatics online.

Motivation: The importance of fast and affordable DNA sequencing methods for current day life sciences, medicine and biotechnology is hard to overstate. A major player is Ion Torrent, a pyrosequencing-like technology which produces flowgrams – sequences of incorporation values – which are converted into nucleotide sequences by a base-calling algorithm. Because of its exploitation of ubiquitous semiconductor technology and innovation in chemistry, Ion Torrent has been gaining popularity since its debut in 2011. Despite the advantages, however, Ion Torrent read accuracy remains a significant concern. Results: We present FlowgramFixer, a new algorithm for converting flowgrams into reads. Our key observation is that the incorporation signals of neighboring flows, even after normalization and phase correction, carry considerable mutual information and are important in making the correct base-call. We therefore propose that base-calling of flowgrams should be done on a read-wide level, rather than one flow at a time. We show that this can be done in linear-time by combining a state machine with a Viterbi algorithm to find the nucleotide sequence that maximizes the likelihood of the observed flowgram. FlowgramFixer is applicable to any flowgram-based sequencing platform. We demonstrate FlowgramFixer’s superior performance on Ion Torrent Escherichia coli data, with a 4.8% improvement in the number of high-quality mapped reads and a 7.1% improvement in the number of uniquely mappable reads. Availability: Binaries and source code of FlowgramFixer are freely available at: http://www.cs.tau.ac.il/~davidgo5/flowgramfixer.html. Contact: li.ca.uat.tsop@5ogdivad

Contributions: We developed a new lossless compression method for WIG data, named smallWig, offering the best known compression rates for RNA-seq data and featuring random access functionalities that enable visualization, summary statistics analysis and fast queries from the compressed files. Our approach results in order of magnitude improvements compared with bigWig and ensures compression rates only a fraction of those produced by cWig. The key features of the smallWig algorithm are statistical data analysis and a combination of source coding methods that ensure high flexibility and make the algorithm suitable for different applications. Furthermore, for general-purpose file compression, the compression rate of smallWig approaches the empirical entropy of the tested WIG data. For compression with random query features, smallWig uses a simple block-based compression scheme that introduces only a minor overhead in the compression rate. For archival or storage space-sensitive applications, the method relies on context mixing techniques that lead to further improvements of the compression rate. Implementations of smallWig can be executed in parallel on different sets of chromosomes using multiple processors, thereby enabling desirable scaling for future transcriptome Big Data platforms. Motivation: The development of next-generation sequencing technologies has led to a dramatic decrease in the cost of DNA/RNA sequencing and expression profiling. RNA-seq has emerged as an important and inexpensive technology that provides information about whole transcriptomes of various species and organisms, as well as different organs and cellular communities. The vast volume of data generated by RNA-seq experiments has significantly increased data storage costs and communication bandwidth requirements. Current compression tools for RNA-seq data such as bigWig and cWig either use general-purpose compressors (gzip) or suboptimal compression schemes that leave significant room for improvement. To substantiate this claim, we performed a statistical analysis of expression data in different transform domains and developed accompanying entropy coding methods that bridge the gap between theoretical and practical WIG file compression rates. Results: We tested different variants of the smallWig compression algorithm on a number of integer-and real- (floating point) valued RNA-seq WIG files generated by the ENCODE project. The results reveal that, on average, smallWig offers 18-fold compression rate improvements, up to 2.5-fold compression time improvements, and 1.5-fold decompression time improvements when compared with bigWig. On the tested files, the memory usage of the algorithm never exceeded 90 KB. When more elaborate context mixing compressors were used within smallWig, the obtained compression rates were as much as 23 times better than those of bigWig. For smallWig used in the random query mode, which also supports retrieval of the summary statistics, an overhead in the compression rate of roughly 3–17% was introduced depending on the chosen system parameters. An increase in encoding and decoding time of 30% and 55% represents an additional performance loss caused by enabling random data access. We also implemented smallWig using multi-processor programming. This parallelization feature decreases the encoding delay 2–3.4 times compared with that of a single-processor implementation, with the number of processors used ranging from 2 to 8; in the same parameter regime, the decoding delay decreased 2–5.2 times. Availability and implementation: The smallWig software can be downloaded from: http://stanford.edu/~zhiyingw/smallWig/smallwig.html, http://publish.illinois.edu/milenkovic/, http://web.stanford.edu/~tsachy/. Contact: zhiyingw@stanford.edu Supplementary information: Supplementary data are available at Bioinformatics online.

In-memory computing provides unprecedented power and area efficiency for the execution of convolutional neural networks by using memory bitcells to perform dot-product (DP) operations in the analog domain. Yet, these operators suffer from analog non-idealities (ANIs) that degrade the inference accuracy. This paper proposes design guidelines inferred from a holistic simulation-based analysis of the impact of ANIs on the accuracy-efficiency trade-off that affects current-domain DP operators based on conventional 6T-SRAM bitcell arrays. We define a custom SNR metric aware of the DP operand distribution to quantify decision errors associated with various ANIs, over ranges of input/output resolution and hardware design parameters. We find out that non-linearity and local mismatch are the dominant ANIs limiting the design space, while IR drops turn out to be critical only when targeting high parallelism. We then quantify the accuracy-efficiency trade-off related to these dominant ANIs across the design space and propose optimal design choices. We notably identify that using larger operators can either improve or worsen the SNR depending on the target output resolution. Furthermore, we show that hardware calibration techniques which mitigate mismatch help to recover a fraction of the lost SNR, with greater effectiveness when scaling down the supply voltage.

This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem. The proposed methodology is composed of: 1) a search heuristic to seek faster and feasible approximate configurations for the architectures under evaluation; 2) low-power techniques regarding hybrid approximate adders design for accelerators based on trees of shift-and-add operations; 3) high-performance evaluation by exploring parallel prefix adders and low power analysis through the use of the adder optimized by a commercial synthesis tool in the precise part of the approximate adders; and 4) energy efficiency analysis by considering both the approximate techniques and voltage over scaling estimation. Furthermore, improvements are proposed for the state-of-the-art approximate adders under evaluation in this paper. Two case studies are considered to assess the proposed methodology: 1) Gaussian image filter and 2) Sobel operator. The precise and approximate image filters were described in very high-speed integrated circuits hardware description language regarding the proposed methodology. Results are shown after synthesis to a 45-nm standard cell-based technology, where energy reductions ranging from 7.7% up to 73.2% were experienced for multiple levels of quality considering the applications under analysis.

Like many others, our institution had to adapt our traditional proctored, written examinations to open-book online variants due to the COVID-19 pandemic. This paper describes the process applied to develop open-book online exams for final year (undergraduate) students studying Applied Machine Learning and Applied Artificial Intelligence and Deep Learning courses as part of a four-year BSc in Computer Science. We also present processes used to validate the examinations as well as plagiarism detection methods implemented. Findings from this study highlight positive effects of using open-book online exams, with 85% of students reporting that they either prefer online open-book examinations or have no preference between traditional and open-book exams. There were no statistically significant differences reported comparing the exam results of student cohorts who took the open-book online examination, compared to previous cohorts who sat traditional exams. These results are of value to the CSEd community for three reasons. First, it outlines a methodology for developing online open-book exams (including publishing the open-book online exam papers as samples). Second, it provides approaches for deterring plagiarism and implementing plagiarism detection for open-book exams. Finally, we present feedback from students which may be used to guide future online open-book exam development.

This paper outlines the longitudinal development of a K-12 outreach model, to promote Computer Science in Ireland. Over a three-year period, it has been piloted to just under 9700 K-12 students from almost every county in Ireland. The model consists of a two-hour camp that introduces students to a range of Computer Science topics: addressing computing perceptions, introduction to coding and exploration of computational thinking. The model incorporates on-site school delivery and is available at no cost to any interested school across Ireland. The pilot study so far collected over 3400 surveys (pre- and post- outreach delivery). Schools from all over Ireland self-selected to participate, including male only, female only and mixed schools. The no-cost nature of the model meant schools deemed "disadvantaged", to private fee-paying schools participated. Initial findings are very positive, including the balance of male and female participants, where in the 2017-18 academic year it was 56:44 and in 2019-20 (to date), it is 35:65 respectively. Once the model is validated and tweaked (based on survey data), the model will be published (open access) for other institutions to implement the model locally. In addition, the authors intend to link schools (that the team have worked with over the three years) with local institutions, thus developing a sustainable ecosystem for the program to continue. This paper describes the model structure and outlines early findings.

Android systems have been successfully developed to meet the demands of users. The following four methods are used in Android systems for memory management: backing swap, CompCache, traditional Linux swap, and low memory killer. These memory management methods are fully functioning. However, Android phones cannot swap memory into solid-state drives, thus slowing the processor and reducing storage lifetime. In addition, the compression and decompression processes consume additional energy and latency. Therefore, the CompCache requires an extension. An extended Android CompCache using a graphics processing unit to compress and decompress memory pages on demand and reduce the latency is introduced in this paper. This paper characterizes each data compression and decompression utility by measuring compression ratio, compression and decompression throughput, and energy efficiency to validate the process. Experimental results prove that data compression and decompression utilities can be beneficial to reduce the latency and perform faster compression and decompression compared with existing approaches

Convolutional neural networks (CNN) is a specialized case of artificial neural networks(ANN) and finds its application in computer vision and parallel distributed computing for processing of massive amount of data generated by sensors and to meet the power constraints of IOT devices. Recent advancements in parameter optimization, regularization techniques, improvement in activation functions, corresponding loss functions, advancements in the coted the research of Convolutonal Neural Network’s(CNN’s) in past few years. Training of neural networks is cumbersome and takes a lot of time can take days or even weeks. This limits the application of Convolutional Neural Network(CNN) in real time research fields where computational speed is of utmost importance. Thus there is a need for appropriate and enhanced computational speed to meet the requirements of these real time applications.This paper describes CNN in detail summarizes architectural evolution of CNN from 1998 to 2019. Three types of strategies have been explained to enhance the computational speed of CNN at algorithmic level and implementation level. This paper gives detailed insight about computation speed acceleration using Stochastic Gradient Decent(SGD) optimization, Fast convolution and exploiting parallelism challenges in CNN posed by these techniques and recent advancements.The paper also includes detailed view of different framework usage while implementing fast convolution or parallelism techniques. The ultimate aim of the paper to explore all such recent techniques by which we can accelerate the training speed of the CNN’s without compromising the accuracy.

Real-time, accurate, and robust localisation is critical for autonomous vehicles (AVs) to achieve safe, efficient driving, whilst real-time performance is essential for AVs to achieve their current position in time for decision making. To date, no review paper has quantitatively compared the real-time performance between different localisation techniques based on various hardware platforms and programming languages and analysed the relations among localisation methodologies, real-time performance and accuracy. Therefore, this paper discusses state-of-the-art localisation techniques and analyses their localisation performance in AV application. For further analysis, this paper firstly proposes a localisation algorithm operations capability (LAOC)-based equivalent comparison method to compare the relative computational complexity of different localisation techniques; then, it comprehensively discusses the relations among methodologies, computational complexity, and accuracy. Analysis results show that the computational complexity of localisation approaches differs by a maximum of about 〖10〗^7 times, whilst accuracy varies by about 100 times. Vision- and multi-sensor fusion-based localisation techniques have about 2–5 times potential for improving accuracy compared with lidar-based localisation. Lidar- and vision-based localisation can reduce computational complexity by improving image registration method efficiency. Multi-sensor fusionbased localisation can achieve better real-time performance compared with lidar- and vision-based localisation because each standalone sensor does not need to develop a complex algorithm to achieve its best localisation potential. Vehicle-to-everything (V2X) technology can improve positioning robustness. Finally, results show that the fusion technique combined with V2X has considerable potential for achieving a cost-efficient localisation solution for AVs.

Building a post-layout simulation performance model is essential in closing the loop of analog circuits, but it is a challenging task because of the high-dimensional space and expensive simulation cost. To facilitate efficient modeling, this paper proposes a Global Mapping Model Fusion (GMMF) technique. The key idea of GMMF is to reuse the schematic-level model trained by the Artificial Neural Network (ANN) algorithm, and combine it with few mapping coefficients to build the post-simulation model. Furthermore, as an efficient global optimization algorithm, differential evolution is applied to determine the optimal mapping coefficients with few samples. In GMMF, only a small number of mapping coefficients are unknown, so the number of post-layout samples needed is significantly reduced. To enhance practical utility of the proposed GMMF technique, two specific mapping relations, i.e., linear or weakly no-linear and nonlinear, are carefully considered in this paper. We conduct experiments on two topologies of two-stage operational amplifier and comparator in different commercial processes. All the simulation data for modeling are obtained from a parametric design framework. A more than 5× runtime speedup is achieved over ANN without surrendering any accuracy.

For the last few years, cases of applying articial intelligence (AI) to engineering activitiestowards sustainability have been reported. Life Cycle Engineering (LCE) provides a potential to systematicallyreach higher and productivity levels, owing to its holistic perspective and consideration of economic andenvironmental targets. To address the current gap to more systematic deployment of AI with LCE (AI-LCE)we have performed a systematic literature review emphasizing the three aspects:(1) the most prevalent AItechniques, (2) the current AI-improved LCE subelds and (3) the subelds with highly enhanced by AI.A specic set of inclusion and exclusion criteria were used to identify and select academic papers fromseveral elds, i.e. production, logistics, marketing and supply chain and after the selection process describedin the paper we ended up with 42 scientic papers. The study and analysis show that there are manyAI-LCE papers addressing Sustainable Development Goals mainly addressing: Industry, Innovation, andInfrastructure; Sustainable Cities and Communities; and Responsible Consumption and Production. Overall,the papers give a picture of diverse AI techniques used in LCE. Production design and Maintenance andRepair are the top explored LCE subelds whereas logistics and Procurement are the least explored subareas.Research in AI-LCE is concentrated in a few dominating countries and especially countries with a strongresearch funding and focus on Industry 4.0; Germany is standing out with numbers of publications. Thein-depth analysis of selected and relevant scientic papers are helpful in getting a more correct picture ofthe area which enables a more systematic approach to AI-LCE in the future. Funding: Adapt 2030 (Adaptive lifecycle design by applying digitalization and AI techniques to production) (Grant Number: 2019-05589)10.13039/501100001858-VINNOVA, Sweden’s Innovation Agency Adapt 2030

Stateful logic through memristor is a promising technology to build Computing-in-Memory (CIM) systems. However, aging-induced degradation of memristors' threshold voltage imposes a major challenge to the reliability and guardbands estimation of memristive CIM systems, especially the Material Implication (IMPLY) logic based CIM systems. In this paper, a novel in-situ aging-aware error monitoring scheme for memristor-based IMPLY logic is proposed. The proposed in-situ error monitoring scheme can achieve faster error detection speed and higher detection accuracy than the straightforward program-verify monitoring scheme. Simulation results under Monte-Carlo simulation show that the proposed monitoring scheme can effectively detect the major operation failures existing in IMPLY logic operations with a detection accuracy up to 99.95%. Moreover, a case study of error monitoring design of 4-bit IMPLY-based adder is carried out. The analysis result exhibits that the proposed in-situ monitoring scheme can achieve 75.2% improvement on the detection speed against the program-verify scheme. Further analysis on a convolution filter in VGG-11 based Binarized Neural Network shows that 74% improvement on the detection speed can also be achieved by using the proposed monitoring scheme, which suggests that the proposed in-situ error monitoring scheme is an efficient solution to improve the reliability of IMPLY-based memristive CIM systems.

Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial. Luckily there are some post-quantum candidates that are assumed to be resistant against future attacks from quantum computers, and NIST is considering standardizing them. Among these candidates, lattice-based cryptography sounds more interesting than others due to the performance results as well as confidence in the security. There are few works in the literature evaluating the performance of lattice-based cryptography in hardware. In this paper, we focus on Cryptographic Suite for Algebraic Lattices (CRYSTALS) key exchange mechanisms known as Kyber and provide an instruction-set hardware architecture and implement on Xilinx Artix-7 FPGA for performance evaluation and testing. Our proposed architecture provides an efficient and high-performance set of components to perform polynomial sampling, number-theoretic transform (NTT), and point-wise multiplication to speed up lattice-based post-quantum cryptography (PQC). This architecture implemented on ASIC outperforms state-of-the-art implementations.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

This paper introduces a network topology identification (TI) method based on deep neural networks (DNNs) for online applications. The proposed TI DNN utilizes the set of measurements used for state estimation to predict the actual network topology and offers low computational times along with high accuracy under a wide variety of testing scenarios. The training process of the TI DNN is duly discussed, and several deep learning heuristics that may be useful for similar implementations are provided. Simulations on the IEEE 14-bus and IEEE 39-bus test systems are reported to demonstrate the effectiveness and the small computational cost of the proposed methodology. This work was supported by the Spanish Ministry of Innovation under Grant PID2019-104449RB-I00. Paper no. TPWRS-01989-2020. Publicado

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced March algorithm is designed to detect all the modeled faults. In one resistor crossbar with $N$ memristors, the enhanced March algorithm requires $8N$ write and $7N$ read operations with negligible hardware overhead. To reduce the test time, a March RC algorithm is proposed based on read operations with new reference currents, which requires $4N+2$ write and $6N$ read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement March RC algorithm with a little area overhead.

The paper proposes a solution to the problem of choosing the size of a cluster in an ultralow latency network. This work is aimed at designing a method for choosing the size of the digital cluster in an ultralow latency network taking into account the lengths of connecting lines. If the linear dimension calculation is based only on the latency requirements without specifics of building the communication line, it negatively affects timing characteristics. This paper shows the method taking into account the communication line features and basing on the fractal dimension estimation of the road network. The proposed method could be used in planning and designing networks with ultralow latencies. Finally, a numerical experiment was carried out, based on the data of electronic maps, which showed that the assessment of the fractal dimension of roads in the network’s service area makes it possible to increase the accuracy of the size of the formed cluster. Moreover, the proposed method can allow you to reduce the error in estimating the length of connecting lines, which without using it can be on average about 30%.

P4 is a domain-specific language to develop the packet processing of network devices. These programs can easily hide errors, therefore we give a solution to analyze them and detect predefined errors in them. This paper shows the idea, which works with the P4 code as a set of components and processes them one by one, while calculating their pre- and postconditions. This method does not only detect errors between the components and their connections, but it is capable to reveal errors, which are hidden in the middle of a component. The paper introduces the method and shows its calculation in an example.

Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm2 area consumption.

A wide range of problems in applied physics and engineering involve learning physical displacement fields from data. In this paper we propose a deep neural network-based approach for learning displacement fields in an end-to-end manner, focusing on the specific case of particle image velocimetry (PIV), a key approach in experimental fluid dynamics that is of crucial importance in diverse applications such as automotive, aerospace and biomedical engineering. The current state of the art in PIV data processing involves traditional handcrafted models that are subject to limitations including the substantial manual effort required and difficulties in generalizing across conditions. By contrast, the deep learning-based approach introduced in this paper, which is based on a recent optical flow learning architecture known as recurrent all-pairs field transforms, is general, largely automated and provides high spatial resolution. Extensive experiments, including benchmark examples where true gold standards are available for comparison, demonstrate that the proposed approach achieves state-of-the-art accuracy and generalization to new data, relative to both classical approaches and previously proposed optical flow learning schemes. Particle image velocimetry is an imaging technique to determine the velocity components of flow fields, of use in a range of complex engineering problems including in environmental, aerospace and biomedical engineering. A recurrent neural network-based approach for learning displacement fields in an end-to-end manner is applied to this technique and achieves state-of-the-art accuracy and, moreover, allows generalization to new data, eliminating the need for traditional handcrafted models.

In the paper, we consider the urgent need to create highly efficient hardware accelerators for machine learning algorithms, including convolutional and deep neural networks (CNN and DNNS), for associative memory models, clustering, and pattern recognition. We show a brief overview of our related works the advantages of the equivalent models (EM) for describing and designing bio-inspired systems. The capacity of NN on the basis of EM and of its modifications is in several times quantity of neurons. Such neural paradigms are very perspective for processing, clustering, recognition, storing large size, strongly correlated, highly noised images and creating of uncontrolled learning machine. And since the basic operational functional nodes of EM are such vector-matrix or matrix-tensor procedures with continuous-logical operations as: normalized vector operations “equivalence”, “nonequivalence”, and etc. , we consider in this paper new conceptual approaches to the design of full-scale arrays of such neuron-equivalentors (NEs) with extended functionality, including different activation functions. Our approach is based on the use of analog and mixed (with special coding) methods for implementing the required operations, building NEs (with number of synapsis from 8 up to 128 and more) and their base cells, nodes based on photosensitive elements and CMOS current mirrors. Simulation results show that the efficiency of NEs relative to the energy intensity is estimated at a value of not less than 1012 an. op. / sec on W and can be increased. The results confirm the correctness of the concept and the possibility of creating NE and MIMO structures on their basis.

Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection process to increase potential profits. However, intensive computations and complicated data flow in the cointegration approach bring challenges to hardware acceleration. In this paper, for the first time, we propose an efficient and hardware-friendly computing scheme to accelerate the Engle-Granger cointegration. Besides, a novel algorithmic strength reduction strategy and approximation methods are used to significantly reduce the complexity of the proposed scheme. Based on the improved algorithm, both FPGA and ASIC accelerators are developed. The implementation results show that our FPGA and ASIC accelerators perform $36\times $ and $207\times $ faster than GPU, respectively. Thus, our design can significantly reduce the latency of the pairs selection process, and make more profit for investors and traders.