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This paper proposes a 2.4-GHz pre-bias RF energy harvesting rectifier with -35-dBm sensitivity for self-powered chips of wireless sensor networks (WSNs) for Internet of Things (IoT) applications. For high sensitivity, a pre-bias topology is presented by designing pre-stage and drive-stage rectifiers separately with multiple antennas. The pre-stage and the bias circuit just provide a proper bias voltage without driving loads. At single drive-stage configuration, -35-dBm sensitivity can be achieved with 2.4-GHz RF input power, 10-MΩ output load and 0.5-V continuous output voltage. When an 1% duty-cycled operating mode is adopted, 25-μW power can be supplied intermittently with 0.5-V output voltage. This proposed circuit is designed in 0.18-μm standard CMOS process.

In this paper, we propose a 16 quadrature amplitude modulated (QAM) backscatter for self-powered chips with a symbol rate of 1 MHz and a 40 Mb/s bit rate in 2.4 GHz Internet of Things (IoT) system. A four-resistor array is implemented to shift amplitude and achieve quadrature amplitude shift keying (QASK). Transmission lines of four different lengths are applied to change backscattering phase and accomplish quadrature phase shift keying (QPSK). Jointly, by applying transmission lines of twelve lengths and resistors of three values, a 16 QAM backscatter is realized, which is compatible with extensive mainstream communication protocols. The whole system is off-chip, completely passive and low-cost, leading to an easy, economic and efficient communication within wireless sensor networks (WSNs).

This paper presents a 7.9 fJ/conversion-step 10-bit 125 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding (S/H) blocks are employed to achieve high performance with low power consumption. The prototype is implemented in 55 nm standard CMOS process, occupying an active area of 0.18 mm × 0.20 mm. Post simulation results show that an SNDR of 54.01 dB and an ENOB of 8.7 bit can be achieved by consuming 0.41 mW of the ADC core from a 1.2 V supply, and a figure of merit (FOM) of 7.9 fJ/conversion-step.

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from −55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1–10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.