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Abstract. The article analyzes the historical periods of development of the taxation system in Soviet times and during the independence of Ukraine. The stages of transformation of the country’s taxation system and the deduction of the development of the national taxation system are outlined. It was found that during the years of independence there were five transformations of the tax system in 1991, 1995, 1999, 2011 and 2015, respectively. The preconditions of each of the specified stages of realization of transformation of system of the taxation are analyzed. Among the key preconditions for transformational changes in certain periods are: rapid deterioration of key macroeconomic indicators, implementation of laws and regulations on the establishment of the tax police and the transformation of the State Tax Administration into a central executive body as a controlling body for legal entities and individuals, changes in the composition and mechanisms of tax calculation, chaos and invalidity of the system of tax benefits, changes in the legalization of the wage fund and in the system of compulsory state social insurance. The functions of taxes as defining concepts of formation of the tax system of the country that were in each period defined above are investigated. The types and role of tax relief as a tool of state tax regulation and stimulation of socio-economic processes are considered. The assessment of the process of transformation of the tax system identified the existing criteria for reform, including diversity, complementarity and consistency, compromise and evolution, the depth of transformation and innovation of the tax system of Ukraine. It is proved that the tools of transformation of the implementation of the taxation system of Ukraine used in these processes did not always correspond to the peculiarities of the socio-economic situation of the country and the tax policy of the state goal and set of tasks of economic strategy. Existing shortcomings in the Ukrainian taxation system hinder economic growth and lead to high economic shadowing. Thus, the application of these tools in the process of transformation of the tax system has partially solved the existing problems, a significant number of identified tasks currently remain unresolved. Keywords: taxation system, taxes, tax deductions, the state budget, taxation. JEL Classification E62 Formulas: 0; fig.: 0; tabl.: 1; bibl.: 18.

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

The implementation of a charge-sensitive amplifier (CSA) based on the МН2ХА030 array chip (AC) with an adjustable conversion factor for processing signals of silicone photomultipliers (SPM) is considered. The developed CSA, named ADPreampl3, contains a fast and slow signal circuit (SC). The fast SC includes a transresistive amplifier-shaper with a base-level adjustment circuit, and a slow SC includes an CSA, a shaper, and a base-level restorer (BLR) circuit. The main advantage of ADPreampl3 amplifier when used in multichannel integrated circuits is the minimum number of elements used, due to the use of the same stages to perform different functions. To correctly simulate the operation of ADPreampl3, taking into account the features of the input signal source, a simplified electrical equivalent circuit of the SPM, applicable to both circuit simulation and measurements, is proposed. Circuit simulation of ADPreampl3 using the proposed equivalent circuit of SPM with a supply voltage of ±3 V, made possible to establish that: fast SC is characterized by the bandwidth up to 60 MHz and allows adjusting the base level in the range from -0.1 V to 0.2 V. Thus, it is possible to compensate the technological variation of the output voltage of the fast SC or set the required switching threshold of the comparator connected to the output of the fast SC; slow SC allows you to adjust the base level in the range from -1 V to 1 V and smoothly change the amplitude of the output signal, including phase inversion, when the control voltage changes from -1 V to 1 V; the BLR circuit provides a constant shape of the output voltage pulse with a DC input current of ADPreampl3, varying in the range of ±190 μA, and a negligible change of the base level at ±20% of the resistance variation of integrated resistors. ADPreampl3 amplifier enables the transition to the ``sleep'' mode with a decrease in current consumption up to 10 μA, maintains operability at an absorbed dose of gamma radiation up to 500 krad and the effect of the integral neutron fluence up to 1013 n/cm2 and can be used in multi-channel signal processing chips of SPM.

The article considers the effect of 60Co gamma rays on the characteristics (the major ones for the analog ICs) of SiGe n-p-n transistors of SGB25V technology: the voltage across the forward-biased base-emitter junction, the dependence of the static base current gain in the common-emitter (CE) configuration on emitter current, the output characteristic in the CE configuration.

The article proposes a method of bandwidth extension of the analog integrated circuit of the variable-gain amplifier (VGA) based on SiGe BiCMOS technology with the rules of 0.18 µm. The designed VGA has a linear (in dB) control characteristic. The authors consider the VGA architecture and present its design outputs. They describe the properties of two modifications of the VGA integrated circuit – with classical correction of the response and with the circuit of the parasitic capacitance cancellation in the high-impedance node. The article shows that the second circuit solution allows increasing the upper frequency limit of the VGA by a factor of 1.8-2.

The current-voltage curves (CVC) of n-p-n SiGe heterojunction bipolar transistors (HBT) are considered within the temperature range from minus -195˚С up to 25˚С, produced on the SGB25V technology of IHP. The experimental setup, the measurement technique and the connection features of transistors for elimination of the self-excitation are described. The special attention is paid to the temperature dependences of the static base current gain βF in the common-emitter configuration (CEC) and to the output CVC characteristics of transistor in the CEC.