1. A low-memory intensive decoding architecture for double-binary convolutional turbo code
- Author
-
Liang Zhou, Jun Wu, and Ming Zhan
- Subjects
Hardware_MEMORYSTRUCTURES ,General Computer Science ,Computer science ,Branch metrics,computational complexity,MAP algorithm,state metrics cache ,Sequential decoding ,Parallel computing ,Data_CODINGANDINFORMATIONTHEORY ,Metrics ,Turbo code ,Branch Metrics ,State (computer science) ,Cache ,Electrical and Electronic Engineering ,Difference-map algorithm ,Decoding methods - Abstract
Memory accesses take a large part of the power consumption in the iterative decoding of double-binary convolutional turbo code (DB-CTC). To deal with this, a low-memory intensive decoding architecture is proposed for DB-CTC in this paper. The new scheme is based on an improved maximum a posteriori probability algorithm, where instead of storing all of the state metrics, only a part of these state metrics is stored in the state metrics cache (SMC), and the memory size of the SMC is thus reduced by 25%. Owing to a compare-select--recalculate processing (CSRP) module in the proposed decoding architecture, the unstored state metrics are recalculated by simple operations, while maintaining near optimal decoding performance.
- Published
- 2014