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High-rate low-density parity-check (LDPC) codes are the focus of intense research in magnetic recording because, when decoded by the iterative sum-product algorithm, they show decoding performance close to the Shannon capacity. However, cycles, especially short cycles, are harmful to LDPC codes. The paper describes the partition-and-shift LDPC (PS-LDPC) codes, a new class of regular, structured LDPC codes that can be designed with large girth and arbitrary large minimum distance. Large girth leads to more efficient iterative decoding and codes with better error-floor properties than random LDPC codes. PS-LDPC codes can be designed for any desired column weight and with flexible code rates. The paper details the girth and distance properties of the codes and their systematic construction and presents analytical and simulation performance results that show that, in the high signal-to-noise ratio region, PS-LDPC codes out- perform random codes, alleviating the error floor phenomenon. [ABSTRACT FROM AUTHOR]

The maximum transition run (MTR) and running digital sum (RDS) constraints have a wide variety of applications in magnetic recording systems. The property of an MTR constraint is to eliminate long runs of transitions so that certain common error events can be eliminated. The property of an RDS constraint is desirable for achieving high-density recording for recording channels exhibiting low frequency components, such as perpendicular recording channels. It is very common to implement more than one constraint in practice to achieve the desired effect in the recording channel. In this paper, the labeled graph representations of RDS and MTR [or the time-varying MTR (TMTR)] constraints are combined to obtain new classes of constraints: RDS-MTR and RDS-TMTR constraints. The capacity of a combined constraint is slightly lower than that of its constituent constraints. The spectra of RDS-MTR and RDS-TMTR constraints show the suppression of low frequency contents compared to the conventional MTR and TMTR constraints. A method for designing block codes is proposed to implement the properties of RDS, MTR (or TMTR), the run-length-limited (RLL) (0, k), and twin constraints. The cardinalities of block codes are maximized over various situations of codeword boundaries. The code design method- ology is demonstrated via a rate 100/108 RDS-TMTR block code based on a rate 20/21 RDS-TMTR mother code. [ABSTRACT FROM AUTHOR]

A parity code and a distance enhancing constrained code are often concatenated with a Reed-Solomon code to form a coding system for magnetic recording. The tensor-product parity coding scheme helps to improve efficiency of the parity code while retaining the same level of performance. In this paper, we present two methods for combining a tensor-product parity code with a distance-enhancing constrained code. The first method incorporates a constrained code with unconstrained positions. The second method uses a new technique, which we call word-set partitioning, to achieve a higher code rate relative to the first method. We simulate the performance of several coding systems based upon the two combination methods on a perpendicular recording channel, and we compare their symbol error rates and sector error rates with those of a system that uses only a Reed-Solomon code. [ABSTRACT FROM AUTHOR]

We have three main goals in this paper. First, we will show the equivalences and relationships among some of the well-known classes of structured low density parity check (LDPC) codes. Second, we consider application of these codes to magnetic recording channel. We will make performance comparisons not only with bit-error-rate (BER) metric but also with sector failure rate (SFR) as the comparison dimension. Such a comparison is more meaningful from a system analysis perspective. Finally, we consider the case of these structured LDPC codes concatenated with conventional Reed-Solomon (RS) codes. We believe LDPC codes will not completely replace RS codes in the future storage devices. From this perspective, for LDPC codes to be contenders for future architectures, they will need to work in harmony with the outer RS codes. This implies that we have to take into account the redundancy introduced by the overall coding scheme, that is, RS code in concatenation with LDPC code, to reach meaningful comparisons from a system design perspective. [ABSTRACT FROM AUTHOR]