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A parity code and a distance enhancing constrained code are often concatenated with a Reed-Solomon code to form a coding system for magnetic recording. The tensor-product parity coding scheme helps to improve efficiency of the parity code while retaining the same level of performance. In this paper, we present two methods for combining a tensor-product parity code with a distance-enhancing constrained code. The first method incorporates a constrained code with unconstrained positions. The second method uses a new technique, which we call word-set partitioning, to achieve a higher code rate relative to the first method. We simulate the performance of several coding systems based upon the two combination methods on a perpendicular recording channel, and we compare their symbol error rates and sector error rates with those of a system that uses only a Reed-Solomon code. [ABSTRACT FROM AUTHOR]

We have three main goals in this paper. First, we will show the equivalences and relationships among some of the well-known classes of structured low density parity check (LDPC) codes. Second, we consider application of these codes to magnetic recording channel. We will make performance comparisons not only with bit-error-rate (BER) metric but also with sector failure rate (SFR) as the comparison dimension. Such a comparison is more meaningful from a system analysis perspective. Finally, we consider the case of these structured LDPC codes concatenated with conventional Reed-Solomon (RS) codes. We believe LDPC codes will not completely replace RS codes in the future storage devices. From this perspective, for LDPC codes to be contenders for future architectures, they will need to work in harmony with the outer RS codes. This implies that we have to take into account the redundancy introduced by the overall coding scheme, that is, RS code in concatenation with LDPC code, to reach meaningful comparisons from a system design perspective. [ABSTRACT FROM AUTHOR]

Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage appli- çations. To apply these codes to digital recording systems, two possible schemes are considered in this paper. In the first scheme, a single LDPC code of column weight j > 2 is used to replace the Reed-Solomon (RS) code of the conventional channel. In the second scheme, an iterative code is used as the inner code and is concatenated with an outer RS code. Single parity check TPC code is considered for this scheme. We developed a high-throughput field programmable gate array (FPGA) platform to evaluate the error floor performance of LDPC codes and the error statistics of TPC codes in partial response (PR) channel with turbo equalization. High rate codes (rate 8/9 for LDPC code and rate 0.935 for TPC code) are evaluated for magnetic recoding application. The bit error rate (BER) performance of LDPC code down to 1010can be reached within 2 h using the FPGA platform. The TPC code error statistics are evaluated using about 1011 bits at different signal-to-noise (SNR) levels. For practical implementation complexity and power consumption, 2 channel iterations and 2 TPC decoder iterations are employed. The results show that the gain by applying TPC code under 2 channel iterations and 2 TPC decoder iterations is marginal. [ABSTRACT FROM AUTHOR]