In this paper we show that it is possible to derive a sequential circuit either from a transition table or from a State Transition Graph (STG), so that the sequential circuit has the short test detecting all multiple stuck-at faults at gate poles of the circuit, and delay of each circuit path is detectable
PATH DELAY FAULT (PDF), EQUIVALENT NORMAL FORM (ENF), LAUNCH-ON-SHIFT (LOS) SCAN TECHNIQUE, НЕИСПРАВНОСТЬ ЗАДЕРЖКИ ПУТИ, РОБАСТНАЯ НЕИСПРАВНОСТЬ ЗАДЕРЖКИ, ЭКВИВАЛЕНТНАЯ НОРМАЛЬНАЯ ФОРМА (ЭНФ), LOS-ТЕХНИКА СКАНИРОВАНИЯ СОСТОЯНИЙ СХЕМЫ, Hardware_PERFORMANCEANDRELIABILITY, Hardware_LOGICDESIGN
Abstract
Structural scan based delay testing is used for detecting the circuit delays. Because of architectural limitations not an each test pair can be applied through a scan delay test. Enhanced scan techniques were developed to remove these restrictions on vector pairs. Unfortunately these techniques have rarely been used in practice because of the near doubling of the flip-flop area. Most promising are partial enhanced scan approaches based on partial selection of flip-flops for including them in enhanced scan chains. The problem is how to select proper flip-flops. In this paper we suggest to estimate flip-flop observability as a probability of robust PDF manifestation for paths connected with corresponding state variable in the frame of the LOS technique. It is desirable to include in enhanced scan chains flip-flops with low observabilities of corresponding state variables. The algorithm of observability calculation is developed and experimental results are presented.
The paper presents a structure of reconfigurable finite state machine (FSM) consisting of the output/next state logic of two basic FSMs, the control unit, and the state register. The state register is shared by two basic FSMs. One of the basic FSMs has a fixed behavior, and another a changeable behavior. The reconfigurable FSM is proven to model the joint behavior of two basic FSMs.
This paper presents a hardware implementation in FPGA (field-programmable gate array) of the Zakrevskij FSM-based cryptosystem. Using developed software, we generate a FSM (Finite State Machine) and build the VHDL code for the FSM. Then using Xilinx WebPack Design Software, we program an FPGA integrated circuit. We have evaluated the implementation in FPGA of the FSMbased cryptosystem from the point of view of state encoding style.
Published
2010
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