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The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from -104.33 to -82.17 dBc/Hz, with tres = 8.64-27.71 ps, TSVG = 143-333 ps, FREF = 20-60 MHz. [ABSTRACT FROM AUTHOR]