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Matrix multiplication is a fundamental operation widely used in science and engineering. There is an approximate matrix multiplication method as a way to reduce the amount of computation of matrix multiplication. Approximate matrix multiplication determines an appropriate probability distribution for selecting columns and rows of matrices, and performs approximate matrix multiplication by selecting columns and rows of matrices according to this distribution. Probability distributions are generated by considering both matrices A and B participating in matrix multiplication. In this paper, we propose a method to generate a probability distribution that selects columns and rows of matrices to be used for approximate matrix multiplication, targeting only matrix A. Approximate matrix multiplication was performed on 1000x 1000 ~ 5000x5000 matrices using existing and proposed methods. The approximate matrix multiplication applying the proposed method compared to the conventional method has been shown to be closer to the original matrix multiplication result, averaging 0.02% to 2.34%. [ABSTRACT FROM AUTHOR]

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs. [ABSTRACT FROM AUTHOR]

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately. [ABSTRACT FROM AUTHOR]