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In this study, the capacitances of strip transmission lines of various thicknesses and widths were accurately calculated using the mode-matching method. To perform the mode-matching method, a strip transmission line structure was modeled, and the potential for the analysis space was expressed by applying the Laplace equation and the principle of superposition. Dirichlet and Neumann boundary conditions were applied to calculate the mode coefficient included in the derived potential expression. Additionally, to verify the validity of the mode-matching analysis, the convergence of the potential for a specific location was confirmed, and the analysis results of the mode-matching method and commercial simulation were compared. Using the verified mode-matching analysis, the change in capacitance according to the thickness and width changes of the strip transmission line was investigated, the capacitance was calculated using the approximate equation, and bar bridging and analysis were performed. From the analysis results, the capacitances calculated using the approximation formula differed depending on the structure of the strip transmission line. The structure of the strip transmission line that needed to be calculated by rigorous electromagnetic analysis was confirmed. This differs from a previous study in that the mode-matching analysis can precisely predict the capacitance corresponding to the geometrical variation of the strip transmission lines. [ABSTRACT FROM AUTHOR]

In this study, we propose a methodology to achieve consistency between EM simulation and measurement results by implementing a BCI-monitoring probe system as an EM model. To accurately model the BCI monitoring probe system using EM, it is necessary to accurately calculate the magnetic permeability μr’(ω) and μr’’(ω), which change according to the frequency of the ferrite constituting the core of the probe. The impedance measured by the BCI and monitoring probe includes the connector impedance and the capacitance component owing to the coil shape of the probe. In this study, a method of extracting the relative permeability of the ferrite core using only the R-L parallel circuit components excluding these components suggests that the EM analysis model was constructed using the magnetic permeability obtained in this way, and the consistency of the reflection characteristics and transmission characteristics of each probe was confirmed. Finally, the EM model of the BCI-monitoring probe system was built to simulate the S-parameters. The average error with the response characteristics of the measured S-parameters was approximately 1.12 dB, and the effectiveness of the perme- ability extraction method and the entire EM model were confirmed. [ABSTRACT FROM AUTHOR]

This paper presents a D-band low-noise amplifier using a 28-nm CMOS process. The low-noise amplifier consists of four differential common-source stages, each adopting a capacitance neutralization technique to improve stability and gain. Impedance matching is implemented using a transformer and a transmission line. To reduce the imbalance in the differential signal, a bypass capacitor was connected to the transformer, and the input and output transformers were optimized for impedance by connecting the capacitance to the single-ended signal path. The measurement shows that the low-noise amplifier exhibits a peak gain of 17.8 dB at 139 GHz and a 3-dB bandwidth of 20 GHz. The total chip area including the pads is 0.4 mm² and the dc power consumption is 50.2 mW. [ABSTRACT FROM AUTHOR]

This study introduces the design of an RF CMOS power amplifier based on a cascode powercell. self-body-biasing (SBB) of common source (CS) transistors (TRs) was proposed to improve the nonlinearity of power amplifiers. Accordingly, an analysis of the linearization principle of SBB was performed through simulation. The SBB technique is configured by inserting a 4 kΩ resistor between the body and the drain of the CS TRs. Accordingly, using the SBB to the CS TRs could achieve the effect of reducing the third-order intermodulation distortions (IMD3) by changing the third-order transconductance (gm3). Moreover, an effect of reducing AM-PM distortions could be achieved by securing a voltage condition in which the CG TRs could operate in a saturation region, which reduces the variation of parasitic capacitances at the output terminal. [ABSTRACT FROM AUTHOR]

In this study, we analyzed the signal characteristic changes in a single-ended dual-stripline configuration, which is often used in high-speed memory system chip packages and module circuit boards, and developed a methodology to mitigate crosstalk. Although using a dual-stripline configuration can result in a reduced number of layers and increased cost of PCB, it inevitably deteriorates the crosstalk and reflection characteristics formed by capacitive coupling. This is because there is no reference layer between the two signal layers. We analyzed the characteristic change according to the self and mutual capacitance values and proposed an airgap structure located between adjacent signal layers to mitigate capacitance and crosstalk by using inhomogeneity. The proposed method was demonstrated to mitigate the signal noise caused by near-end and far-end crosstalk not only in a single coupled line but also in a multi-coupled line and actual structure with micro-stripline and vias. [ABSTRACT FROM AUTHOR]

A novel analysis and design method for an ultrawideband transition structure between a microstrip and parallel stripline based on conformal mapping is proposed. The line capacitance of each cross-sectional area along the transition is calculated by applying the Schwarz–Christoffel transformation, and the corresponding characteristic impedance is derived analytically. To design the proposed transition structure with ultrawideband operation, a 50-Ω characteristic impedance is maintained throughout the transition sections. Measured and simulated results show excellent performance, with an insertion loss of less than 1 dB and return loss of more than 10 dB from DC to 40 GHz. [ABSTRACT FROM AUTHOR]

In this study, we propose a method for improving the accuracy of the characteristic impedance extraction method of line standards when using multiline thru-reflect-line(mTRL) calibration on chips based on the propagation constant method. This method uses a substrate with corrected dielectric properties to obtain a result that is close to the value of the measured propagation constant, which is obtained by mTRL calibration without using basic substrate information when determining the capacitance per unit length using electromagnetic simulation. We observed a slight improvement in the accuracy of the proposed method. This improvement was verified by comparing the results with a commercial off-chip impedance standard in a low-frequency band. In addition, we compared the method of obtaining the characteristic impedance only with the electromagnetic simulation results and demonstrated the accuracy limit of the low-frequency band using this method. Finally, the intrinsic characteristics of transistors were determined using a fabricated complementary metal-oxide-semiconductor transistor. [ABSTRACT FROM AUTHOR]

Three types of metal-oxide-metal capacitors fabricated in a 65-nm CMOS process are compared. The HPP structure utilizing only the vertical electric field exhibits a higher capacitance density of 0.2, 0.64, and 0.76 fF/μm2 as the number of stacked metal layers increase to four, six, and eight, respectively. The VPP structure, which utilizes only the horizontal electric field, exhibits a relatively small capacitance density of 0.27 fF/μm2. In contrast, the PW structure using the vertical and horizontal electric fields exhibits the highest capacitance density of 0.88 fF/μm2. In the given CMOS process, it is observed that the HPP structure with many metal layers and the PW structure are advantageous at millimeter-wave frequencies, offering a suitable replacement for metal-insulator-metal capacitors. [ABSTRACT FROM AUTHOR]

This study presents a four-stage common-source(CS) differential low-noise amplifiers at the 80 GHz band developed by using the 65-nm complementary metal–oxide–semiconductor(CMOS) process. To improve the gain of CS structures in the millimeter wave band, the Cgd capacitance between the gate and the drain is neutralized by using a cross-coupled MOS capacitor. By varying the Well bias configuration of MOS capacitor, the characteristics of the amplifier is observed, and the optimal bias condition is derived to achieve maximum gain and high stability. The implemented circuit showed a maximum gain of 28.43 dB at 83.2 GHz and a simulated noise figure of 6.89 dB. The low noise amplifier consumes 50 mW direct current(DC) power from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

Herein, a non-Foster matching circuit is designed to improve the impedance matching characteristics of small antennas in the VHF and UHF bands. The proposed non-Foster circuit is designed to operate with negative capacitance in a wide frequency band from 50 MHz to 1,000 MHz for use in various communication bands. To ensure the stability of the non-Foster circuit with conditional stability, the open-circuit stability condition of Linvill was satisfied, and the circuit was fabricated using the FR-4 substrate. The fabricated non-Foster circuit was combined with a small antenna to verify its performance by measuring the return loss and received power in the FM, DMB, and GSM bands. The measured return loss was improved from -6 dB to -30 dB, and the measured received power was improved from 0.5 dBm to 5.2 dBm. [ABSTRACT FROM AUTHOR]