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Diese Arbeit beschäftigt sich mit fehlertoleranten Radnabenantrieben mit integrierter Leistungselektronik für Elektrofahrzeuge. Die Besonderheit des betrachteten Fahrzeugtyps ist, dass die Bremsfunktion an den angetriebenen Rädern vollständig von den Radnabenantrieben übernommen wird, sodass an diesen Rädern keine zusätzlichen Reibungsbremsen notwendig sind. Im Rahmen der Arbeit wird für diese Anwendung zunächst eine optimale Topologie für den elektrischen Antriebsstrang ermittelt. Auf dieser Topologie aufbauend wird im nächsten Schritt ein Sicherheitskonzept für den Leistungsteil des elektrischen Antriebsstrangs entwickelt. Zur Umsetzung dieses Sicherheitskonzepts werden anschließend zwei neu entwickelte Verfahren zur halbleiternahen Erkennung von Halbbrückenkurzschlüssen vorgestellt und untersucht. Darüber hinaus wird eine Methodik zur Berechnung der Zwischenkreisbelastung entwickelt. Diese ermöglicht eine vereinfachte Berechnung der im Betrieb auftretenden Belastungen unter Berücksichtigung der Wechselwirkungen zwischen den verteilten leistungselektronischen Komponenten.

To avoid large fluctuations of the dc-link voltage of switched reluctance drives, usually large capacitors are used. To achieve this, electrolytic capacitors providing high capacitance densities are typically employed. As these particular devices are prone to deterioration, they frequently cause failures and thereby reduce the overall life time of the drive. It is therefore subject of current research to diminish the minimum necessary amount of capacitance for a safe operation of the drive, in order to make the utilization of alternative capacitor technologies possible. In this thesis, two novel approaches are being presented, which allow for a significant reduction of the stress on the dc-link capacitor of a switched reluctance drive. Starting from a comprehensive investigation of different typical load cases, the commutation process of phase currents, which is a characteristic trait of switched reluctance motors, is being identified as the main reason for a low-frequency current strain of the dc-link capacitor. The proposed methods help reduce the load on the dc-link capacitor significantly only by means of control and do therefore not require any modifications of the machine or the drive. Both strategies influence the current waveform of the outgoing phase during the commutation process in such a way that the charge being fed back into the dc-link capacitor is minimized. The first method is based on pulse width modulation and varies the duty cycle of the outgoing phase during commutation to keep the charge in the dc-link capacitor constant during every PWM period. Besides very small residual voltage fluctuations in the dc-link, it can be shown by investigations of the frequency spectrum of the dc-link current that the stress on the dc-link capacitor is completely eliminated at the fundamental electrical frequency. In addition to that, comprehensive computer simulations are carried out to show that the proposed control method does not compromise important performance criteria, such as efficiency or torque ripple. The second introduced control scheme is based on hysteresis control and can be integrated into a conventional current hysteresis control without great efforts. In this approach, the dc-link voltage is observed by a hysteresis controller, which controls the switches of the outgoing phase in such a way that the dc-link voltage stays below a pre-defined limit during commutation. It is shown that this scheme does not degrade the performance of the drive as well. This thesis is concluded by an experimental validation of the proposed control methods on a test stand. Measurements of the dc-link voltage prove that both approaches lead to a significant reduction of the ripple voltage compared to conventional control structures. The remaining ripple voltage of the pulse width modulation scheme is slightly smaller compared to the hysteresis control, which makes it better suited for a combination with controls requiring a constant dc-link voltage.