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This paper presents the results and the limits of 1-D analytical modeling of electrostatic potential in the low-doped p type silicon body of the asymmetric n-channel DG SOI MOSFET, where the contribution to the asymmetry comes only from p- and n-type doping of polysilicon used as the gate electrodes. Solving Poisson's equation with boundary conditions based on the continuity of normal electrical displacement at interfaces and the presence of a minimum electrostatic potential by using the Matlab code we have obtained a minimum potential with a slow variation in the central zone of silicon with the value pinned around 0.46 V, where the applied VGS voltage varies from 0.45 V to 0.95 V. The paper states clearly the validity domain of the analytical solution and the important effect of the localization of the minimum electrostatic potential value on the potential variation at interfaces as a function of the applied VGS voltage.

We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.

Einwandige Kohlenstoff Nanoröhrchen können sowohl halbleitende als auch metallische Eigenschaften aufweisen, je nachdem wie die Röhrchenachse im Vergleich zur Anordnung der Kohlenstoffatome verläuft. Dies wird durch den sogenannten Aufrollvektor bestimmt. Halbleitende Nanoröhrchen können für Transistoren (CNFETs) verwendet werden, deren Verhalten sich mit einer modifizierten Version von Berkeley Spice 3f5 simulieren läßt. Die aus diesen Simulationen gewonnenen Parameter werden zur Parametrisierung von SystemC Modellen aus CNFETs bestehender Grundschaltungen verwendet, was zu einer um Größenordnungen höheren Simulationsgeschwindigkeit bei hoher Genauigkeit führt. Single walled carbon nanotubes (CNT) can be either metallic or semiconducting depending on the tube's orientation in relation to the configuration of the carbon atoms. This is determined by the so-called chiral vector. Semiconducting CNT can be used in transistors (CNFET) which can be simulated by a modified version of Berkeley Spice 3f5. The parameters determined by these simulations are used to parameterise SystemC models of some basic building blocks yielding fast simulations with high accuracy.

This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35µm 3Metal/2Poly CMOS technology and the chip area is approximately 70µm × 110µm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.