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The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

The Kangxi Southern Inspection Tours strengthened the Qing Dynasty's control over Jiangnan Buddhism, thereby promoting the standardization and officialization of Jiangnan temples and externalizing imperial power through images and physical space. Taking Jinshan Temple as an example, this study combines spatial analysis of architecture and image analysis used by art historians to examine the transformation between physical and pictorial spaces in Jinshan Temple, revealing the spatial operation of imperial power. The intervention of imperial power sparked the space reconstruction of Jinshan Temple through a process of "merger-occupation-infiltration-adjustment". Thus, the control measures of Kangxi are revealed, including the emphasis on the geographical significance of the temple, space occupation of royal buildings, change in landscape, and the adaptation of monks by adjusting their imagination of the sacred space. By determining the spatial reconstruction, we observe that the spatial strategy of power reflects Kangxi's religious attitude toward Buddhism of "neither promoting nor suppressing, but treating it reasonably" 朕惟置之焉能有無之間, which may enrich our understanding of the influence of Kangxi's Southern Inspection Tours on Jiangnan's religious space. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions. [ABSTRACT FROM AUTHOR]

This article focuses on the relationship between body, scale, and space, as revealed in Mogao Cave 254 in Gansu Province. Three topics, namely, body scale, pilgrim behavior, and time–space perception, are discussed. A space model based on mapping and measurement by former scholars is created to facilitate and visualize the analysis of the body scale of the cave space; the restriction of body scale suggests certain pilgrim behavior in the cave, whereas the occurrence of body behavior results in perception in the dimension of time. How time and space are related must be understood to comprehend the motif of Buddhist expression. This study is an architectural approach to spatial analysis that integrates the design, construction, and use phases through the scale, behavior, and perception dimensions. It is dedicated to broadening and enriching the cognitive dimensions of the space value of Mogao caves to reveal the original value of caves as religious spaces and completely preserve their material and invisible cultural heritage. [ABSTRACT FROM AUTHOR]

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions. [ABSTRACT FROM AUTHOR]

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits. [ABSTRACT FROM AUTHOR]

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%–99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%–86.85% (46.01%–55.96%), 66.89%–73.25% (29.41%–38.49%), 68.02%–74.20% (41.40%–52.20%), 60.60%–68.18% (18.09%–33.18%), and 75.86%–80.52% (3.05%–20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay. [ABSTRACT FROM AUTHOR]

In this brief, a non-invasive online solution for 2.5D IC based on distributed pulse shrinking is proposed to test the faults of interconnects. Furthermore, a regression model based on artificial neural network (ANN) is proposed in order to judge whether the interconnects are faulty and quantify the degree of the faults in real time by online monitoring the delay of interconnects. Experiments on defect detection are presented through HSPICE simulation with realistic models for 45nm CMOS technology. The results show that the proposed method has features including: high resolution, low area overhead, high robustness, and be able to predict the class and the fault size. [ABSTRACT FROM AUTHOR]

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively. [ABSTRACT FROM AUTHOR]

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively. [ABSTRACT FROM AUTHOR]

In this brief, a cobweb-based redundant through-silicon-via (TSV) design is proposed with efficient hardware as well as high repair rate to repair clustered faulty TSVs (FTSVs). The experimental simulation results demonstrate that for highly clustered faults, the repair rate of the proposed RTSV method is 48.59% and 1.75% higher than that of the ring-based and router-based RTSV methods, respectively. Furthermore, the proposed design can achieve 63.93% and 16.34% hardware reductions compared with the router-based and the ring-based design, respectively. [ABSTRACT FROM AUTHOR]

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency. [ABSTRACT FROM AUTHOR]

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all. [ABSTRACT FROM AUTHOR]

This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant storage nodes, the cell achieves the following robustness: 1) In the case of 1 being stored, the cell can self-recover from any double-node upset (DNU) as well as any single node upset (SNU); 2) in the case of 0 being stored, the cell can self-recover from any double-adjacent-node upset (DANU), partial double-separated-node upset (DSNU) as well as any SNU. Any other DSNU can be tolerated by the cell due to the use of the layout approach. Second, a layout-independent cell is proposed that can self-recover from any DNU as well as any SNU. Simulation results validate the robustness of the proposed cell designs. Furthermore, compared with typical existing radiation hardened memory cells, the proposed layout-dependent cell saves 55.60% read access time and 33.76% write access time at the costs of 4.28% power dissipation and 39.01% silicon area on average, still low compared with layout-independent cell designs. [ABSTRACT FROM AUTHOR]

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs. [ABSTRACT FROM AUTHOR]

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages. [ABSTRACT FROM AUTHOR]

Technology scaling results in that, soft errors, due to radiation‐induced single event double‐upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU‐immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high‐performance, low‐cost, and fully SEDU‐immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating‐based triple path DICE and a multiple‐input Muller C‐element. Simulation results demonstrate the SEDU‐immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS‐SEUT latch. [ABSTRACT FROM AUTHOR]

Mount Putuo in Zhejiang Province, China, is the most important holy land of Guanyin in East Asia. Landscape sacralization is a key modality by which sacred meaning is constructed. This paper takes several examples—the Tidal Sound Cave ("chaoyin dong" 潮音洞), the Well of the Immortal Mei ("Meixian jing" 梅仙井), the Well of Ge Hong ("Ge Hong jing" 葛洪井), the Well of the Immortal ("xianren jing" 仙人井), and Duangu Pier ("Duan Gu daotou" 短姑道頭)—to analyze the three types of processes of sacralization. The Tidal Sound Cave is a re-construction of the founding myths; Well of the Immortal Mei, the Well of Ge Hong and the Well of the Immortal reflect harmony between local legends of Daoist immortals and the sacred Buddhist site; and the Duangu Pier accomplished its sanctification process in the course of local pilgrimage activities. By sorting out the mechanism and process of landscape sanctification and exploring the generation and renewal of landscape meaning, we can observe the logic of the construction of this sacred site. [ABSTRACT FROM AUTHOR]

This article explores regional Buddhist monasteries in Tang Dynasty (618–907 CE) China, including their arrangement, functions, and sources for their study. Specifically, as a case study, it considers the reconstruction of the Kaiyuan monastery 開元寺 in Sizhou 泗州 (present-day Jiangsu Province) with reference to the works of three prominent state officials and scholars: Bai Juyi 白居易 (772–846), Li Ao 李翱 (772–841), and Han Yu 韓愈 (768–824). The writings of these literati allow us to trace the various phases of the monastery's reconstruction, fundraising activities, and the network of individuals who participated in the project. We learn that the rebuilt multi-compound complex not only provided living areas for masses of pilgrims, traders, and workers but also functioned as a barrier that protected the populations of Sizhou and neighboring prefectures from flooding. Moreover, when viewed from a broader perspective, the renovation of the Kaiyuan monastery demonstrates that Buddhist construction projects played a pivotal role in the social and economic development of Tang China's major metropolises as well as its regions. [ABSTRACT FROM AUTHOR]