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This article presents a survey of the different modern high-level synthesis (HLS) design space exploration (DSE) techniques that have been proposed so far to automatically generate hardware accelerators of different tradeoffs. HLS has multiple advantages compared to traditional RT-level-based hardware design. One key advantage is that a variety of different microarchitectures of unique tradeoffs can be obtained from the same untimed behavioral description by setting different synthesis options. Out of all the possible microarchitectures, the one that the designers are most interested in are the Pareto-optimal ones. The main problem is that the search space grows superlinearly with the number of synthesis options, and hence, heuristics have been proposed to search the space efficiently. This article summarizes the main techniques proposed and addresses the critical issues still not resolved as well identifies new opportunities in this field. It also serves as a guide for anyone wanting to create their own HLS DSE. [ABSTRACT FROM AUTHOR]

In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this article is that configurations optimized when targeting ASICs are often, as we will show in this article, highly un-optimal when remapped onto an FPGA. Thus, this article proposes a method to first generate a variety of dataflow configurations targeting an ASIC given multiple behavioral descriptions for high-level synthesis (HLS) and then, based on a compositional predictive model, automatically reoptimize the dataflow when mapped onto an FPGA. The experimental results show that our proposed method works well and that it is very fast. [ABSTRACT FROM AUTHOR]

This paper studies the acceleration of numerical simulations executed on Field-Programmable Gate Arrays (FPGAs) for electric machines presented by voltage-behind-reactance (VBR) models. In VBR models, the stator dynamics are modeled in abc coordinates, while the rotor dynamics are formulated in qd reference frame. Both induction motors and synchronous generators, operating without and with magnetic saturation, are considered. Once VBR models of these machine types are reviewed, their dynamic models are discretized using Runge-Kutta numerical routines. The detailed mapping of such discrete models to FPGA is provided using High-Level Synthesis, which directly converts untimed descriptions into VHDL or Verilog. An automated method finds the fastest FPGA architecture by finding the best set of synthesis options. Experimental results show that our FPGA-based acceleration flow leads to about 92-168 times average simulation speed-up for various machine types compared to the MATLAB simulation. [ABSTRACT FROM AUTHOR]

Many applications show tolerance to inaccuracies. These can be exploited to build faster circuits with smaller area and lower power. This is particularly true for the hardware accelerators in heterogeneous computing systems. A major problem with approximate computing is that the resulting approximated circuit is highly dependent on the training data. Previous works often rely on static training results. If the workload is dynamic in nature or changes over time, output errors may reach unacceptable levels. Therefore, dynamic control methods are needed to solve this problem. To address this issue, in this paper, we propose an approximate self-adaptive architecture that autotunes itself at runtime based on the workload. Two different control mechanisms are proposed, one based on a regular heartbeat (HB), which resets the approximate circuits at regular intervals and the other based on internal lightweight checkers (LWCs). These checkers detect a change in the workload and reset the approximations. Experimental results show that our proposed methods work well leading to very good results compared to other approximation methods while keeping the output error within the given maximum error threshold at relatively low-area overheads, on average 8% and 8.5% for HB and LWC method, respectively, and delay overheads 5.9% and 8.1%. [ABSTRACT FROM AUTHOR]

Many classes of applications exhibit significant tolerance to inaccuracies in their computations. Some examples include image processing, multimedia applications, and machine learning. These inaccuracies can be exploited to build circuits with smaller area, lower power, and higher performance. Most previous work restricts the approximate optimizations to a particular level of abstraction or step within the VLSI process. This paper shows that a combined multilevel approach is far more superior. Thus, this paper exploits different optimizations visible only at each particular level, leading to better results than single-level methods. Moreover, approximate computing is highly data-dependent. Therefore, in this paper, we study the stability of the approximate circuits when the circuit is optimized for a particular data distribution and the final workload differs from it. Previous work mainly considers a single input data distribution and that this distribution is equal to the final workload. Results show that our proposed method can find better and more optimal configurations compared with previous work and can achieve circuits, which are more robust in environments with dynamic workloads. [ABSTRACT FROM AUTHOR]

This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systems-on-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock. [ABSTRACT FROM PUBLISHER]

One of the biggest advantages of C-Based VLSI design over traditional RT-level design is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. So far previous works have focuses on either pruning the design space or by creating predictive models in combination with different metaheuristics. In this letter, we present a hierarchical method which makes use of modern HLS tool’s options to synthesize functions as functional operators in order to explore these separately. Our method therefore explores each function separately and then performs a merging stage in order to obtain the overall dominating results. Moreover our proposed method detects if any changes in the behavioral description have happened between two exploration executions and only explores those functions which have been affected by the source code changes, while the results of the previous exploration are reused, thus enabling for incremental DSE. Results show that our method is very efficient. [ABSTRACT FROM PUBLISHER]

High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness. [ABSTRACT FROM PUBLISHER]

This paper presents a clustering method called clustering design space exploration (CDS-ExpA) to accelerate the architectural exploration of behavioral descriptions in C and SystemC. The trade-offs between faster exploration versus optimality of results are investigated. Two variations of CDS-ExpA were developed: CDS-ExpA(min) and CDS-ExpA(max). CDS-ExpA(min) builds the smallest possible clusters while CDS-ExpA(max) builds the largest possible ones, reducing further the design space. Results show that CDS-ExpA(min) and CDS-ExpA(max) explore the design space 90% and 92% faster on average than a previously developed annealer-based exploration, method, at the expense of not finding 36% and 47% of the Pareto optimal designs and finding the smallest design that is 7% and 9% on average, larger, and the fastest design 28% and 32% slower, respectively. [ABSTRACT FROM AUTHOR]

Abstract-This paper proposes a new solution to the problem of eliminating hotspots from gate-level netlists as well as examines the effects of timing constraints on the temperature reduction and the overall temperature flattening on the chip. Our core technique consists of three steps. First, a thermal analysis is carried out for logic netlists. (The netlists are assumed to be either isolated or embedded in a larger system with macro-cells.) We then apply a new technique, called isothermal logic partitioning technique (LP-temp), to the netlists, which essentially builds isothermal `logic clusters for the netlists and splits each of the logic clusters exceeding the maximum allowed temperature through its hottest point. This will enlarge a contact point for the hotspot to cool down. Finally, the entire system is replaced using a custom designed temperature-aware floorplanner so that the temperature across the entire system is reduced and flattened. We have developed a thermal-aware design flow, integrating our thermal-aware logic partitioning technique with a timing and thermal-aware floorplanner. Two cases were analyzed: (tight timing) LP-ternp combined with the timing and thermal-aware floorplanner, where the partitioned units by LP-ternp are replaced locally considering a tight timing budget (5% timing degradation); (loose timing) L P-tern p combined with thermal-aware replacement, considering a loose timing budget (10% timing degradation). From experimentations using a set of benchmark designs, it is confirmed that our temperature reduction technique is effective, generating designs with an average of 5.54% and 9.9% more reduction of peak temperature (on average) for the cases of tight and loose timing than that of the designs by a conventional thermal-aware floorplanner without using LP-temp, respectively. We also analyzed the effect of our proposed technique on field-programmable gate arrays (FPGAs) in order to contrast its effectiveness on systems with hotspots on hardmacros. Results show that our technique can reduce the temperature in these systems on average 3.40% and 6.61% for the case of loose and tight timing constraints respectively compared to the thermal-aware floorplanner without using LP-ternp. [ABSTRACT FROM AUTHOR]