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Optical deep learning (DL) accelerators have attracted significant interests due to their latency and power advantages. In this article, we focus on incoherent optical designs. A significant challenge is that there is no known solution to perform single-wavelength accumulation (a key operation required for DL workloads) using incoherent optical signals efficiently. Therefore, we devise a hybrid approach, where accumulation is done in the electrical domain, and multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently. Through detailed design and evaluation of our design, along with a comprehensive benchmarking study against state-of-the-art RRAM-based designs, we derive the following key results: (1) For a four-layer multilayer perceptron network, our design achieves 115× and 17.11× improvements in latency and energy, respectively, compared to the RRAM-based design. We can take full advantage of the speed and energy benefits of the optical technology because the inference task can be entirely mapped onto our design. (2) For a complex workload (Resnet50), weight reprogramming is needed, and intermediate results need to be stored/re-fetched to/from memories. In this case, for the same area, our design still outperforms the RRAM-based design by 15.92× in inference latency, and 8.99× in energy. [ABSTRACT FROM AUTHOR]

As technology size scales down, magnetic tunnel junctions (MTJs) as a promising technology are becoming more and more sensitive to process variation, especially in oxide barrier thickness. Process variation particularly affects the cell resistance and the critical switching current for the smaller dimensions. This article proposes an MTJ cell with one free and two pinned layers, which highly improves the process variation robustness. By employing the spin transfer torque (STT)-spin-Hall effect (SHE) switching method, our proposed MTJ cell improves the switching speed and lowers the switching power consumption. Per simulations, an MRAM cell built with the proposed MTJ cell offers up to 36% lower total power consumption, up to 32% higher write performance, and 35% higher read performance over the previous state-of-the-art MRAMs. Also, the error rate resulting from process variation is 1.4%, which is about one-tenth of the best examples reported in the literature. [ABSTRACT FROM AUTHOR]

Approximate computing (AC) is a recently emerged computing paradigm that can trade in accuracy for power, area, and delay in accuracy-insensitive applications, such as image processing. Magnetic tunnel junction (MTJ) cells can further these AC advancements as a result of their near-zero current leakage. In addition, due to the non-volatility of MTJs, an MTJ-based circuit can switch into a completely OFF state during idle cycles for further power savings without loss of data or the need for extra components. In this article, two novel MTJ-based approximate full-adder circuits are proposed and evaluated. The proposed 1 bit adder circuits are then extended to an 8 bit accuracy-adaptive adder that dynamically adjusts the level of accuracy as needed. For evaluations, we have employed the proposed accuracy-adaptive adder in the implementation of a Gaussian image processing filter. We have observed that, at the expense of a tolerable loss of accuracy, the proposed accuracy-adaptive adder offers up to 47% and 94% improvements in power and performance, respectively, when compared to its conventional accurate counterparts. [ABSTRACT FROM AUTHOR]

Content-addressable memories (CAMs) are widely used for data-centric applications where one must search for data patterns. CMOS CAMs can incur large areas and, hence, power consumption. Nonvolatile (NV) devices, such as ferroelectric field-effect transistors (FeFETs) and resistive random access memories, have been used in the design of NV CAMs to improve both logic density and power consumption. To further improve logic density, this article proposes a compact, multistate CAM (MCAM) that can store 3 bits in a cell using just one FeFET and three FinFETs per cell. Moreover, the proposed MCAM does not require a precharging phase for search as is typical with other CAM designs, which can lead to improved performance. Simulations with experimentally calibrated 22-nm FeFET and 22-nm FinFET technology models suggest that the proposed 3T1Fe-MCAM can perform up to 7.1× faster search operations with up to 28.8× lower area–energy–delay product compared with state-of-the-art ternary/analog CAM designs. To show that the proposed MCAM array can accurately detect all worst case matches/mismatches, we design an MCAM array with 11 cells per row (to represent a 32-bit number). We also study how the nonidealities related to programming/search voltages impact performance metrics and show that the proposed MCAM can tolerate up to 15-mV noise during programming and up to 20-mV noise on search voltages even in a worst case match/mismatch. [ABSTRACT FROM AUTHOR]

In this article, four novel approximate full-adder (AXFA) circuits based on the emerging magnetic tunnel junction (MTJ) device is proposed. The proposed magnetic FAs (MFAs) offer full nonvolatility, low area, and considerably lower energy consumption than their previous counterparts. Also, two of the proposed MFAs have the advantage of single event upset (SEU) tolerance. Simulation results reveal that the proposed designs offer over 50% energy efficiency in comparison with the considered previous fully nonvolatile MFAs. Using the proposed adders in the design of an approximate Gaussian filter, we showed that the filtered noisy images have almost the same results as the accurate Gaussian filter. The proposed MFAs have an accurate carry-out output and an approximate sum output with an error distance of 2. [ABSTRACT FROM AUTHOR]

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features to overcome the aforesaid issues of CMOS technology. The hybrid MTJ/CMOS circuits offer low power consumption, nonvolatility, and high performance. This paper proposes two novel hybrid MTJ/CMOS approximate full-adder circuits (AXMA) for low power approximate computing-in-memory architectures. The proposed AXMAs offer low area, high sensing speed, considerable lower energy consumption, and the lowest power delay product (PDP) than the considered antecedent counterparts. The proposed AXMAs also introduce the advantage of full nonvolatility to the systems. This feature allows the system to be powered off during the idle modes in order to reduce the static power without the need for any retention parts or loss of data. Applications of the proposed AXMAs in digital image processing and their effect on the quality of images considering some relevant metrics like peak signal-to-noise ratio (PSNR) and mean structural similarity (MSSIM) are also investigated using the MATLAB software. [ABSTRACT FROM AUTHOR]

As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today's logic circuits. Emerging spin-based logic circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show a great potential to overcome the aforementioned issues. However, radiation induced soft errors are still a problem in MTJ-based circuits as they need sequential peripheral CMOS circuits for sensing the MTJs. This paper proposes a novel nonvolatile and low-cost radiation hardened magnetic full adder (MFA). In comparison with the previous designs, the proposed MFA is capable of tolerating particle strikes regardless of the amount of charge induced to a single node and even multiple nodes. Besides, the proposed MFA offers low power operation, low area and high performance as compared with previous counterparts. One of the most important features suggested by the proposed MFA circuit is full nonvolatility. Nonvolatile logic circuits remove the cost of high volume data transactions between memory and logic and also facilitate power gating in logic-in-memory architectures. [ABSTRACT FROM AUTHOR]

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated. [ABSTRACT FROM AUTHOR]

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts. [ABSTRACT FROM AUTHOR]

This paper proposes a new magnetic random access memory (MRAM)-backed SRAM (MSRAM) cell to be used in structure of programmable logic devices such as field programmable gate array (FPGA). The proposed cell contains a fast SRAM part and also a backup MRAM part. An FPGA based on the proposed MSRAM cell will offer good performance, very low power consumption, and also nonvolatility. Besides, by increasing the number of MRAM parts, it can offer the capability of multiple design implementations. Furthermore, facilitating power gating and tolerance to radiation-induced soft errors are of other advantages offered by the proposed design. [ABSTRACT FROM PUBLISHER]

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins. [ABSTRACT FROM AUTHOR]

Very large-scale integrated circuit design, based on today’s CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leakage power and bring the advantage of nonvolatility. However, radiation-induced soft error is still an issue in such new designs as they need peripheral CMOS components. As a result, these magnetic-based circuits are still susceptive to radiation effects. This paper proposes a radiation hardened and low power magnetic full-adder (MFA) for advanced microprocessors. Comparing with the previous work, the proposed MFA is capable of tolerating any particle strike regardless of the induced charge. Besides, our MFA circuit offers a lower energy consumption in write operation as compared with previous counterparts. We also suggest an incremental modification to the proposed MFA circuit to give it the advantage of full nonvolatility for future nonvolatile microprocessors. [ABSTRACT FROM PUBLISHER]

Field-programmable gate arrays (FPGAs) based on static random access memory (SRAM) are more common than other types, including flash and anti-fuse, because of their infinite configurability and high performance. However, following the scaling down of CMOS technology, standby power of the CMOS circuits are becoming crucial. Logic circuits based on magnetic RAM (MRAM) can be an attractive replacement for SRAM-based logics thanks to their zero leakage and CMOS compatibilities. Furthermore, in FPGA design, using MRAM logics instead of SRAM logics results in some more advantages including non-volatility and high radiation reliability. In this paper, effects of radiation-induced soft errors on MRAM-based FPGAs (MFPGAs) are taken into account. Soft error tolerance of the previous MFPGAs are discussed and a new MFPGA structure is proposed. It is shown that the proposed non-volatile, low-power, and high-speed MFPGA is highly robust against radiation-induced soft errors. It is also shown that the proposed MFPGA offering a high radiation robustness does not incur a considerable design overhead compared with the other similar MFPGAs. [ABSTRACT FROM PUBLISHER]

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) that are mostly employed as high-performance and high-density memory cells are prone to radiation-induced single-event upsets. Therefore, designing reliable SRAM cells has always been a serious challenge. In this paper, we propose two novel SRAM cells, namely, RHD11 and RHD13, that provide more attractive features than their latest proposed counterparts. Simulation results show that our proposed SRAM cells as compared with some state-of-the-art designs have considerably higher robustness against single-event multiple effects. Moreover, they offer a sensible area overhead advantage so that our proposed RHD11 SRAM cell has 19.9% smaller area than the prominent dual-interlocked cell. The simulation results and analyses show that our proposed SRAM cells, particularly the proposed RHD13, have a considerable lower failure probability among the considered recent radiation-hardened SRAM cells. [ABSTRACT FROM PUBLISHER]

Magnetoresistive memories, such as spin-transfer torque random access memory and magnetic latches (M-latch), are emerging memory technologies that offer attractive features, such as high density, low leakage, and nonvolatility as compared with conventional static memory. In this paper, we have proposed two single-event upset tolerant M-latch circuits in which their CMOS peripheral circuits are robust against radiation effects. Similar to the conventional M-latch circuit, our proposed M-latches employ two magnetic tunnel junction elements. Therefore, they consume almost the same energy consumption in comparison with nonprotected M-latch circuit. The simulation results of comparison with previous work show that our proposed radiation hardened M-latches consume less energy, occupy less area, and in case of a particle strike, offer lower restoring time. Furthermore, we have thoroughly investigated the robustness of our proposed radiation-hardened M-latches against single-event multiple effects and also in the presence of process variation as serious reliability challenges in emerging nanometer scale technologies. [ABSTRACT FROM AUTHOR]

Following the scale down of complementary metal-oxide semiconductor (CMOS) technology, radiation-induced soft errors have become a concerning issue in CMOS circuit design. Today’s integrated circuits suffer from single event double node upset (SEDU) that takes place when an energetic particle strike affects two adjacent nodes. In this letter, a magnetic random access memory block capable of tolerating SEDUs is proposed and evaluated. The proposed circuit utilizes a hybrid design of magnetic and CMOS-based technology that considerably reduces the static power, improves the performance, and offers the advantage of nonvolatility. Simulation results validated that the proposed circuit is fully single event upset and also SEDU immune beside the other advantages offered. [ABSTRACT FROM PUBLISHER]

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the e®ects of process and temperature variations on di®erent design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least e®ects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations. [ABSTRACT FROM AUTHOR]

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propa-gation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% difference) while offering lOOOx speedup as compared with MC-based simulation. [ABSTRACT FROM AUTHOR]