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Abstract This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics.

Abstract One of the key problems in designing and implementing graph analysis algorithms for distributed platforms is to find an optimal way of managing communication flows in the massively parallel processing network. Message‐passing and global synchronization are powerful abstractions in this regard, especially when used in combination. This paper studies the use of a hardware‐implemented refutable global barrier as a design optimization technique aimed at unifying these abstractions at the API level. The paper explores the trade‐offs between the related overheads and performance factors on a message‐passing prototype machine with 49,152 RISC‐V threads distributed over 48 FPGAs (called the Partially Ordered Event‐Triggered Systems platform). Our experiments show that some graph applications favour synchronized communication, but the effect is hard to predict in general because of the interplay between multiple hardware and software factors. A classifier model is therefore proposed and implemented to perform such a prediction based on the application graph topology parameters: graph diameter, degree of connectivity, and reconvergence metric. The presented experimental results demonstrate that the correct choice of communication mode, granted by the new model‐driven approach, helps to achieve 3.22 times faster computation time on average compared to the baseline platform operation.

Objective: Analysis of the literature shows that the number of patients with chronic renal failure (CRF) increases every year. To date known more than twenty renal diseases, the end of clinical manifestation of which is CRF. Studies of recent years show that in CRF genesis and progression leading role plays arterial hypertension, smoking, age, male sex, dyslipidemia, diabetes mellitus, some autoimmune diseases, metabolic disorders of calcium and phosphorus, the use of nephrotoxic drugs, the effects of psycho-emotional and oxidative stress, malfunction of the renin-angiotensin-aldosterone system, etc. At the present stage, for diagnosis of violations of the glomerular filtration rate, ordered ten, most important of them - Cystatin C method. Another non-invasive method is doppler ultrasound. In spite of this, the issues of early diagnosis of chronic kidney disease remain to the end not studied and not solved, which requires the development of new working algorithms.

Objective: The study of the waterway transmission as dominant, with the spread of intestinal infections. Methods: A retrospective analysis of the journals for the registration of infectious diseases, maps of epidemiological checkups of typhoid foci, dysentery, diarrheal diseases, infectious hepatitis A (HAV) for 1980-2015, as well as reports of the Republican and regional CSSES (Center for State Sanitary and Epidemiological Surveillance) on infectious diseases were carried out. Results: The dominance of the water factor under conditions of the specific weight of Flexner shigellosis during the period of under study ranged between 75-85%. Compared with typhoid fever and bacterial dysentery, the incidence of diarrhoea in the country during the analyzed period remains at a high enough level – from 629.0 to 1206.3, and in 2015, it rose sharply and reached 2150 per 100 thousand. The indicators for the Regions of Republican Subordination, Gorno-Badakhshan Autonomous Region and Khatlon Region varied the broad mass of the population. The performed complex of sanitary-epidemiological evaluation paths and transmission factors identified the dominant value of an aqueous (90%) and a minor role contact-domestic (6.2%) and food (3.8%) of acute intestinal infections transmission routes among the population. Conclusion: Typhoid fever, acute intestinal infections, dysentery, hepatitis A in the Republic of Tajikistan are a typical aquatic infection associated with the constant activity of the waterway transmission, which often causes large epidemic outbreaks.

Objective: Conduct an analysis of the clinical-epidemic process of HIV infection amongst the population and convicted individuals, and the development of the preventive measures to persons in the risk groups. Methods: 3000 maps of epidemiological survey of the nidus of HIV-infection viruses among the population were analyzed, including 500 maps of the epidemiological survey amongst convicted for 2007-2012 periods, and 1 342 043 of express-testing of HIV-infection among the population, including 37 417 amongst convicted were conducted. As a result, 752 HIV-positive people were identified, of whom 356 were among those convicted. Results: The epidemic mostly affected people aged 20-39 (83%) of the total number of HIV-infected people registered in 2012 among the civilian population. As of July 1, 2008, the share of the sexually transmitted diseases, according to registration, accounted for 25.1% of cases, in 2012 – 30.1 %, in 2016 – 42.4%. In penitentiary institutions, among injected prisoners in 2012 was 92.3%, and the sexual way – 7.0%, and in 2016 – 91.2% and 7.5% respectively. Conclusion: Comparison data on the incidence of HIV infection among the population of the Republic of Tajikistan with registered data amongst convicted established essential distinctions. Counteraction is the priority of the HIV/AIDS agents and methods of non-specific prevention. Providing the risk group with information on the character of the behavior associated with HIV transmission, its change over time in certain areas improves the prognosis of the spread of HIV infection and allows analyzing the effectiveness of preventive and anti-epidemic measures.

Contemporary embedded systems may execute multiple applications, potentially concurrently on heterogeneous platforms, with different system workloads (CPU- or memory-intensive or both) leading to different power signatures. This makes finding the most energy-efficient system configuration for each type of workload scenario extremely challenging. This paper proposes a novel run-time optimization approach aiming for maximum power normalized performance under such circumstances. Based on experimenting with PARSEC applications on an Odroid XU-3 and Intel Core i7 platforms, we model power normalized performance (in terms of instruction per second (IPS)/Watt) through multivariate linear regression (MLR). We derive run-time control methods to exploit the models in different ways, trading off optimization results with control overheads. We demonstrate low-cost and low-complexity run-time algorithms that continuously adapt system configuration to improve the IPS/Watt by up to 139% compared to existing approaches.

This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]

This article reports on the European Digital Kitchen, an EU-funded language learning project which promotes learning of languages, cultures and cuisines in digital interactive kitchens. The project involves taking a normal kitchen and specifically adapting it for language learning using the next generation of digital technology, namely activity recognition and sensor technology. We intend that learners will be able to learn aspects of the language whilst performing a meaningful real-world task and will simultaneously experience the cultural aspect of learning to cook a foreign dish. The article starts by outlining the project background, including rationale, motivation and aims. We then explain in detail how the technology works (using photographs) and outline our design methodology, which blends Task-Based Language Teaching (TBLT) and Human-Computer Interaction (HCI). We then present 3 extracts of Digital Kitchen interaction to illustrate the type of learning which takes place.

One of the key problems in designing and implementing graph analysis algorithms for distributed platforms is to find an optimal way of managing communication flows in the massively parallel processing network. Message‐passing and global synchronization are powerful abstractions in this regard, especially when used in combination. This paper studies the use of a hardware‐implemented refutable global barrier as a design optimization technique aimed at unifying these abstractions at the API level. The paper explores the trade‐offs between the related overheads and performance factors on a message‐passing prototype machine with 49,152 RISC‐V threads distributed over 48 FPGAs (called the Partially Ordered Event‐Triggered Systems platform). Our experiments show that some graph applications favour synchronized communication, but the effect is hard to predict in general because of the interplay between multiple hardware and software factors. A classifier model is therefore proposed and implemented to perform such a prediction based on the application graph topology parameters: graph diameter, degree of connectivity, and reconvergence metric. The presented experimental results demonstrate that the correct choice of communication mode, granted by the new model‐driven approach, helps to achieve 3.22 times faster computation time on average compared to the baseline platform operation. [ABSTRACT FROM AUTHOR]

Performance and energy efficiency considerations have shifted computing paradigms from single-core to many-core architectures. At the same time, traditional speedup models such as Amdahl's Law face challenges in the run-time reasoning for system performance and energy efficiency, because these models typically assume limited variations of the parallel fraction. Moreover, the parallel fraction, which varies dynamically in workloads, is generally unknown at run-time without application-level instrumentation. This article describes novel performance/energy trade-off models based on realistic architectural considerations, which describe the parallel fraction and speedup as functions of performance counter values available in modern processors, removing the need for application-level instrumentation. These are then used to develop a Parallelization-Aware Run-time Management (PARMA) approach. PARMA aims at controlling core allocations and operating voltage/frequency points for energy efficiency, according to the varying workload parallel fractions. The efficacy of our models and the PARMA approach is extensively validated using a number of PARSEC benchmark applications, involving two performance/energy trade-off metrics: energy-delay-product (EDP), typically used in high-performance applications and energy per instruction (EPI), suitable for energy-aware applications. Up to 48 and 68 percent improvements in EDP and EPI have been observed using the PARMA approach compared with parallelization-agnostic methods. [ABSTRACT FROM AUTHOR]

For over 50 years, Amdahl's Law has been the hallmark model for reasoning about performance bounds for homogeneous parallel computing resources. As heterogeneous, many‐core parallel resources continue to permeate into the modern server and embedded domains, there has been growing interest in promulgating realistic extensions and assumptions in keeping with newer use cases. This study aims to provide a comprehensive review of the purviews and insights provided by the extensive body of work related to Amdahl's law to date, focusing on computation speedup. The authors show that a significant portion of these studies has looked into analysing the scalability of the model considering both workload and system heterogeneity in real‐world applications. The focus has been to improve the definition and semantic power of the two key parameters in the original model: the parallel fraction (f) and the computation capability improvement index (n). More recently, researchers have shown normal‐form and multi‐fraction extensions that can account for wider ranges of heterogeneity, validated on many‐core systems running realistic workloads. Speedup models from Amdahl's law onwards have seen a wide range of uses, such as the optimisation of system execution, and these uses are even more important with the advent of the heterogeneous many‐core era. [ABSTRACT FROM AUTHOR]

This article studies the interplay between the performance, energy, and reliability (PER) of parallel-computing systems. It describes methods supporting the meaningful cross-platform analysis of this interplay. These methods lead to the PER software tool, which helps designers analyze, compare, and explore these properties. The web extra at https://youtu.be/aijVMM3Klfc illustrates the PER (performance, energy, and reliability) tool, expanding on the main engineering principles described in the article. [ABSTRACT FROM PUBLISHER]

Contemporary embedded systems may execute multiple applications, potentially concurrently on heterogeneous platforms, with different system workloads (CPU- or memory-intensive or both) leading to different power signatures. This makes finding the most energy-efficient system configuration for each type of workload scenario extremely challenging. This paper proposes a novel run-time optimization approach aiming for maximum power normalized performance under such circumstances. Based on experimenting with PARSEC applications on an Odroid XU-3 and Intel Core i7 platforms, we model power normalized performance (in terms of instruction per second (IPS)/Watt) through multivariate linear regression (MLR). We derive run-time control methods to exploit the models in different ways, trading off optimization results with control overheads. We demonstrate low-cost and low-complexity run-time algorithms that continuously adapt system configuration to improve the IPS/Watt by up to 139% compared to existing approaches. [ABSTRACT FROM AUTHOR]

The choice of radix is crucial for multivalued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multivalued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesize logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to first estimate the potential of the new approach and to second analyze its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show that the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices. [ABSTRACT FROM AUTHOR]