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Despite of the fact that thousands of CD-SEM (critical dimension scanning electron microscope) images are acquired in a daily basis in a fab, limited metrology is performed. Usually these images will not serve other purposes after they are collected and measured, but as they are stored, post-process analysis can be applied. Initially, most of these images are used to perform CD metrology, even though many other types of metrics could be extracted from the same images, especially when using contour metrology. In this paper two use cases will be explored, where contour-based image processing is performed on typical inline metrology targets. In both cases, initial intended metric was CD but thanks to contour based image computing, complementary information can be extracted. In the first use case, CD and overlay metrics can be extracted, while in the second CD, etch slanting and asymmetry analysis is performed across the wafer. Contour-based metrology offers new capabilities to dissociate several layers (e.g. via and line) or elements (e.g. top and bottom) in the image so that interlayer and intralayer metrics, other than width dimensions, can be computed. Besides, a solution not integrated in the tool provides excellent versatility to re-process images, thus allowing the obtention of new metrics, which can be very helpful also for retro-analysis.

Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

International audience; The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching.

Porous materials such as ultra low-k dielectrics are commonly used in micro and nano technologies. Since porosity leads to an increased sensitivity of the material to etching and post-etching plasma processes, porosity, pore size and surface modifications need to be assessed during material integration. In this work, the recently developed Scatterometric Porosimetry technique using a porosimetry acquisition coupled with a scatterometric analysis is applied to measure the properties of porous patterned layers. Measurements are performed on specially fabricated gratings after exposure to different plasma treatments. A side-by-side comparison between Ellipsometric Porosimetry and Scatterometric Porosimetry is carried out on different plasma-treated samples and shows a different impact of the plasma processes on patterned materials compared with blanket films. These results highlight the interest of Scatterometric Porosimetry to characterize sidewall damage after each step of the process. It also appears as a good complementary technique to Ellipsometric Porosimetry which only allows quantitative measurements on continuous layers.

International audience; The use of a metallic hard mask approach for porous dielectric film integration implies for patterning processes, different difficulties like dimensional control, bottom line roughness and residue formation or chamber conditioning. In this paper we propose to present these issues and associated solutions for p-SiOCH integration in dual damascene structure using a trench first metallic hard mask approach.

International audience; For the sub-32 nm node, porous SiCOH dielectrics (p-SiCOH) are integrated using dual damascene patterning by etching trenches and vias into the porous material. One challenge is to control the process conditions to minimize the plasma-induced damage of p-SiCOH materials at the bottom and at the sidewall of the trenches. Ellipsometric Porosimetry has been adapted to characterize the plasma-treated materials for both horizontal and vertical surfaces. Since surface modifications can cause adsorption and desorption delays and hydrophobicity loss, porosimetry measurements operated with multi-solvent and kinetic protocols are required. Quantitative measurements of vertically patterned materials are demonstrated using periodic structures of porous material and a Scatterometric Porosimetry analysis. Results show a good sensitivity of the measurement to the different process conditions but also highlight a different impact of the plasma processes on patterned materials compared with blanket films.

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

International audience; Porous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) can lead to an extrinsic roughening mechanism, such as micromasking caused by metallic particles originating form the titanium nitride mask.

A new technique, so called “scatterometric porosimetry” (SP) has been developed to improve our knowledge on the properties of porous material patterned structures. None of the existing techniques is able to characterize the porous material structures after patterning. SP is based on the measurement of the refractive index variation of porous material structures (lines and holes) when filled with a solvent (toluene, methanol, and water). This technique is applied to monitor the modifications in low-K dielectric materials (porous SiOCH) after the plasma patterning steps used to form lines and vias in the porous materials in a typical dual damascene CMOS technology process.

International audience; For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO2 hard mask may lead to severe profile distortions, attributed to TiFx compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.

A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.