188 results on '"Pradhan, D.K."'
Search Results
2. Nanocrystalline gallium ferrite: A novel material for sensing very low concentration of alcohol vapour
3. DeSyRe: On-demand system reliability
4. Dielectric and impedance spectroscopy of zirconium modified (Na0.5Bi0.5)TiO3 ceramics
5. Effect of Co substitution on the magnetic properties of BiFeO3
6. Catalytic application of CeO2–CaO nanocomposite oxide synthesized using amorphous citrate process toward the aqueous phase one pot synthesis of 2-amino-2-chromenes
7. Solution combustion synthesis and physicochemical characterization of ZrO 2–MoO 3 nanocomposite oxides prepared using different fuels
8. Solid polymer electrolytes based on polyethylene oxide and lithium trifluoro- methane sulfonate (PEO–LiCF 3SO 3): Ionic conductivity and dielectric relaxation
9. Derivation of reduced test vectors for bit-parallel multipliers over GF([2.sup.m])
10. Wavelet fuzzy combined approach for fault classification of a series-compensated transmission line
11. LPRAM: a novel methodology for low-power performance RAM design with testability
12. Verilog-A based effective complementary resistive switch model for simulations and analysis
13. The DeSyRe Project: On-Demand System Reliability.
14. A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems.
15. Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
16. BCH code based multiple bit error correction in finite field multiplier circuits.
17. A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
18. Fault diagnosis in multi layered De Bruijn based architectures for sensor networks.
19. On the synthesis of attack tolerant cryptographic hardware.
20. A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
21. Improved Yield in Nanotechnology Circuits Using Non-square Meshes.
22. Layout-aware Illinois Scan design for high fault coverage coverage.
23. P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.
24. On the design of different concurrent EDC schemes for S-Box and GF(p).
25. A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.
26. Investigating the impact of NBTI on different power saving cache strategies.
27. Improving reliability for bit parallel finite field multipliers using Decimal Hamming.
28. Multiple Bit Error Detection and Correction in GF Arithmetic Circuits.
29. A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization.
30. An Efficient De Bruijn Graph Based Fault Tolerant Sensor Networks Design.
31. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m).
32. Single ended 6T SRAM with isolated read-port for low-power embedded systems.
33. Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
34. A novel error correction technique for adjacent errors.
35. A fast error correction technique for matrix multiplication algorithms.
36. Single element correction in sorting algorithms with minimum delay overhead.
37. A Technique to Identify and Substitute Faulty Nodes in Wireless Sensor Networks.
38. Multiple SEU tolerance in LUTs of FPGAs using protected schemes.
39. Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
40. Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
41. A nano-CMOS process variation induced read failure tolerant SRAM cell.
42. Fault tolerant bit parallel finite field multipliers using LDPC codes.
43. Failure analysis for ultra low power nano-CMOS SRAM under process variations.
44. A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
45. Pseudo parallel architecture for AES with error correction.
46. De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
47. Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
48. A Galois Field Based Logic Synthesis Approach with Testability.
49. Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
50. Single Error Correcting Finite Field Multipliers Over GF(2m).
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.