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Your search keyword '"Pelloie, Jean-Luc"' showing total 11 results
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11 results on '"Pelloie, Jean-Luc"'

1. A new generation of IC processing: Low-power, high-performance SOI CMOS. (Materials (SOI))

Author

Pelloie, Jean-Luc and Auberton-Herve, Andre

Subjects
Semiconductor industry, Integrated circuit design, Circuit designer, Transistors -- Research, Circuit design -- Research, Metal oxide semiconductor field effect transistors -- Research, Semiconductor industry -- Research, Transistor circuits -- Research
Abstract

OVERVIEW To take full advantage of the SOI structure, device architecture and design issues must be addressed. While circuit design is achieved with standard CAD tools, specific modeling is required […]

Published
2001

2. Design myths surround strained SOI

Author

Pelloie, Jean-Luc

Subjects
Market trend/market analysis, Integrated circuit design, Circuit designer, Circuit design -- Forecasts and trends, Silicon-on-isolator -- Design and construction
Published
2004

4. Hot-Carrier Effects and Reliable Lifetime Prediction in Deep Submicron N- and P-Channel SOI MOSFET's.

Author

Renn, Shing-Hwa and Pelloie, Jean-Luc

Subjects
*SILICON-on-insulator technology, *METAL oxide semiconductor field-effect transistors, *HOT carriers, *SCIENTIFIC experimentation
Abstract

Presents information on a study which investigated the hot-carrier effects in deep submicron N- and P-channel silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors. Experimental details; Results and discussion of the study; Conclusions.

Published
1998
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5. Generation-recombination transient effects in partially...

Author

Munteanu, Daniela, Weiser, Douglas A., Cristoloveanu, Sorin, Faynot, Oliver, Pelloie, Jean-Luc, and Fossum, Jerry G.

Subjects
METAL oxide semiconductor field-effect transistors, SILICON-on-insulator technology
Abstract

Presents a study which described a family of gate-induced transient effects that can occur in floating-body partially depleted metal oxide field effect transistor (MOSFET). Experimental methods; Spice model including body thermal generation; Simulation results; Conclusion.

Published
1998
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6. Hot-carrier effects and lifetime prediction in off-state...

Author

Renn, Shing-Hwa, Rauly, Emmanuel, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
HOT carriers, SILICON-on-insulator technology, METAL oxide semiconductor field-effect transistors
Abstract

Investigates hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action in deep submicron N-channel silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Experimental details; Experimental results and numerical simulations; Conclusion.

Published
1998
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7. A Physically Based Relation Between Extracted Threshold Voltage and Surface Potential Flat-Band Voltage for MOSFET Compact Modeling.

Author

Benson, James, D'Halleweyn, Nele V., Redman-White, William, Easson, Craig A., Uren, Michael J., Faynot, Olivier, and Pelloie, Jean-Luc

Subjects
METAL oxide semiconductors, SEMICONDUCTORS, METAL oxide semiconductor field-effect transistors, FIELD-effect transistors
Abstract

Presents information on a study which established compact metal oxide semiconductor (MOS) models. Threshold voltage of a MOS field-effect transistors; Qualitative features of a threshold model; Experimental evaluation; Conclusion.

Published
2001
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8. SOI CMOS requires complex modeling.

Author

Pelloie, Jean-Luc

Subjects
*SILICON-on-insulator technology, *MICROPROCESSORS
Abstract

Focuses on the impact of silicon-on-insulator on high-speed microprocessors. Causes of the decline of threshold voltage; Mechanisms of ionization current; Importance of transistors in gate-tunneling current.

Published
2002

10. Cost Impact of Switching From Bulk to SOI.

Author

Pelloie, Jean-Luc

Subjects
COST effectiveness, SILICON-on-insulator technology, COMPLEMENTARY metal oxide semiconductors, ENERGY consumption, RANDOM access memory, TRANSISTORS, SEMICONDUCTOR industry
Abstract

Focuses on the cost effectiveness of switching from bulk substrates to silicon-on-insulator (SOI) complementary metal oxide semiconductors. Percentage of total power consumption and the die area reduced by using SOI at the 90 nanometer mode; Advantages of new concepts such as the floating-body embedded dynamic random access memory cell using only one SOI transistor.

Published
2006

11. Silicon-On-Insulator Technology Bumps Up SoC Performance.

Author

Pelloie, Jean-Luc and Auberton-Herve, Andre

Subjects
*INTEGRATED circuits, *SILICON-on-insulator technology, *SYSTEMS on a chip, *ELECTRONICS
Abstract

Features the innovative enhancements supportingsilicon-on-insulator (SOI) for systems-on-a-chip. Optimization ofSOI design processes and methodologies; Advantage in using SOI;Various features and characteristics of SOI. INSET: HIGHLIGHTS:.

Published
2003

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