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Through a combination of analytical and numerical minimization procedures, a converter design that results in the minimum total converter loss (including core loss, winding loss, capacitor and energy-storage-reactor loss, and various losses in the semiconductor switches) is obtained. Because the initial phase involves analytical minimization, the computation time required by the subsequent phase of numerical minimization is considerably reduced in this combination approach. The effects of various loss parameters on the optimum values of the design variables are also examined.

Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.

Small-signal models are derived for the power stage of the voltage step-up (boost) and the current step-up (buck) converters. The modeling covers operation in both the continuous-mmf mode and the discontinuous-mmf mode. The power stage in the regulated current step-up converter on board the Dynamics Explorer Satellite is used as an example to illustrate the procedures in obtaining the small-signal functions characterizing a regulated converter.

Closed-form analytical solutions for the design equations of a minimum-mass reactor for a two-winding voltage-or-current step-up converter are derived. A quantitative relationship between the three parameters - minimum total reactor mass, maximum output power, and switching frequency - is extracted from these analytical solutions. The validity of the closed-form solution is verified by a numerical minimization procedure. A computer-aided design procedure using commercially available toroidal cores and magnet wires is also used to examine how the results from practical designs follow the predictions of the analytical solutions.

The current and voltage waveshapes associated with the power transitor and the power diode in an example current-or-voltage step-up (buck-boost) converter were analyzed to highlight the problems and possible tradeoffs involved in the design of high voltage high power converters operating at switching frequencies in the range of 100 Khz. Although the fast switching speeds of currently available power diodes and transistors permit converter operation at high switching frequencies, the resulting time rates of changes of current coupled with parasitic inductances in series with the semiconductor switches, produce large repetitive voltage transients across the semiconductor switches, potentially far in excess of the device voltage ratings. The need is established for semiconductor switch protection circuitry to control the peak voltages appearing across the semiconductor switches, as well as to provide the waveshaping action require for a given semiconductor device. The possible tradeoffs, as well as the factors affecting the tradeoffs that must be considered in order to maximize the efficiency of the converters are enumerated.

This paper presents an algorithm and equations for designing the energy-storage reactor for dc-to-dc converters which are constrained to operate in the discontinuous-reactor-current mode. This design procedure applied to the three widely used single-winding configurations: the voltage step-up, the current step-up, and the voltage-or-current step-up converters. A numerical design example is given to illustrate the use of the design algorithm and design equations.

Implementations of a state-plane-trajectory control law for energy storage dc-to-dc converters are presented. Performance characteristics of experimental voltage step-up converter systems employing these implementations are reported and compared to theoretical predictions.

It recently has been shown in the literature that many dc-to-square-wave parallel inverters which are widely used in power-conditioning applications can be grouped into one of two families. Each family is characterized by an equivalent RLC network. Based on this approach, a classification procedure is presented for self-oscillating parallel inverters which makes evident natural relationships which exist between various inverter configurations. By utilizing concepts from the basic theory of negative resistance oscillators and the principle of duality as applied to nonlinear networks, a chain of relationships is established which enables a methodical transfer of knowledge gained about one family of inverters to any of the other families in the classification array.

A new procedure for the selection of magnetic cores for use in energy-storage dc-to-dc power converters which eliminates the need for an automated computer search algorithm and stored data file is presented. The converter configurations included in the procedure are the three commonly encountered single-winding converters for voltage step-up, for current step-up and for voltage step-up/current step-up, and for the two-winding converter for voltage step-up/current step-up. For each converter configuration, three types of controllers are considered - constant-frequency, constant on-time and constant off-time. Using concepts developed from analyses of these converters by considering the transfer of energy by means of an energy-storage inductor or transformer, a special table of parameters calculated from magnetic core data is constructed and leads to a considerably simplified design procedure.

An investigation of the behavior of the power-conditioning system as a whole is a necessity to ensure the integrity of the aggregate system in the case of space applications. An approach for conducting such an investigation is considered. A description is given of the application of a general digital analog simulator program to the study of an aggregate power-conditioning system which is being developed for use on the International Ultraviolet Explorer spacecraft. The function of the direct energy transfer system studied involves a coupling of a solar array through a main distribution bus to the spacecraft electrical loads.

A digital computer simulation technique, which can be used to study such composite power-conditioning systems, was applied to a spacecraft direct-energy-transfer power-processing system. The results obtained duplicate actual system performance with considerable accuracy. The validity of the approach and its usefulness in studying various aspects of system performance such as steady-state characteristics and transient responses to severely varying operating conditions are demonstrated experimentally.

A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.

Small-signal modeling techniques are used in a system stability analysis of a breadboard version of a complete functional electrical power system. The system consists of a regulated switching dc-to-dc converter, a solar-cell-array simulator, a solar-array EMI filter, battery chargers and linear shunt regulators. Loss mechanisms in the converter power stage, including switching-time effects in the semiconductor elements, are incorporated into the modeling procedure to provide an accurate representation of the system without requiring frequency-domain measurements to determine the damping factor. The small-signal system model is validated by the use of special measurement techniques which are adapted to the poor signal-to-noise ratio encountered in switching-mode systems. The complete electrical power system with the solar-array EMI filter is shown to be stable over the intended range of operation.

The proposed dc model for bipolar junction power switching transistors is based on measurements which may be made with standard laboratory equipment. Those nonlinearities which are of importance to power electronics design are emphasized. Measurements procedures are discussed in detail. A model formulation adapted for use with a computer program is presented, and a comparison between actual and computer-generated results is made.

The use of MOSFETs in a high-frequency high-power dc-to-dc converter is investigated. Consideration is given to the phenomena associated with the paralleling of MOSFETs and to the effect of stray circuit inductances on the converter circuit performance. Analytical relationships between various time constants during the turning-on and turning-off intervals are derived which provide estimates of plateau and peak levels during these intervals.

A model describing the turning-on period of a power switching transistor in an energy storage voltage step-up converter is presented. Comparisons between an experimental layout and the circuit model during the turning-on interval demonstrate the ability of the model to closely predict the effects of circuit topology on the performance of the converter. A phenomenon of particular importance that is observed in the experimental circuits and is predicted by the model is the deleterious feedback effect of the parasitic emitter lead inductance on the base current waveform during the turning-on interval.

A procedure is presented for designing air-gapped energy-storage reactors for nine different dc-to-dc converters resulting from combinations of three single-winding power stages for voltage stepup, current stepup and voltage stepup/current stepup and three controllers with control laws that impose constant-frequency, constant transistor on-time and constant transistor off-time operation. The analysis, based on the energy-transfer requirement of the reactor, leads to a simple relationship for the required minimum volume of the air gap. Determination of this minimum air gap volume then permits the selection of either an air gap or a cross-sectional core area. Having picked one parameter, the minimum value of the other immediately leads to selection of the physical magnetic structure. Other analytically derived equations are used to obtain values for the required turns, the inductance, and the maximum rms winding current. The design procedure is applicable to a wide range of magnetic material characteristics and physical configurations for the air-gapped magnetic structure.

Mathematical representations of a state-plane switching boundary employed in a state-trajectory control law for dc-to-dc converters are derived. Two approaches to implementing the control law are discussed; one approach employs a digital processor and the other uses analog computational circuits. Performance characteristics of experimental voltage step-up dc-to-dc converters operating under the control of each of these implementations are presented.

A recently proposed state-trajectory control law for a family of energy-storage dc-to-dc converters has been implemented for the voltage step-up configuration. Two methods of realization are discussed; one employs a digital processor and the other uses analog computational circuits. Performance characteristics of experimental voltage step-up converters operating under the control of each of these implementations are reported and compared to theoretical predictions and computer simulations.

Using data on standard magnetic-material properties and standard core sizes for air-gap-type cores, an algorithm designed for a computer solution is developed which optimally determines the air-gap length and locates the quiescent point on the normal magnetization curve so as to yield an inductor design with the minimum number of turns for a given ac voltage and frequency and with a given dc bias current superimposed in the same winding. Magnetic-material data used in the design are the normal magnetization curve and a family of incremental permeability curves. A second procedure, which requires a simpler set of calculations, starts from an assigned quiescent point on the normal magnetization curve and first screens candidate core sizes for suitability, then determines the required turns and air-gap length.

Description of an on-line optimal (in the sense of linear minimum mean square error) sequential bit synchronizer assuming minimal a priori knowledge of the incoming data. The adaptive synchronization algorithms, implemented on a small computer, are capable of accurately estimating pulse transition time, pulse amplitude, and pulse width by invoking the powerful Gauss-Markov theorem. Numerous simulations indicate that the performance of the synchronizer is satisfactory from the point of view of the amount of data required and the speed of convergence.

Hybrid cross correlation telemetry data processing system design for decoding pulse frequency modulation

Circuit for linear voltage amplitude to pulse width conversion using controlled unijunction monostable multivibrator

Circuit for remote digital control of frequency synthesizers, giving schematic diagram

Data processing by cross correlation techniques to decode PFM signals from IMP satellites

Design of simple circuit for high speed transmission gating of analog signals with fast switching diode and small overshoot

This paper presents an adaptive estimation algorithm for bit synchronization, assuming that the parameters of the incoming data process are time-varying. Experiment results have proved that this synchronizer is workable either judged by the amount of data required or the speed of convergence.