Search

Nearest neighbor (NN) search computations are at the core of many applications such as few-shot learning, classification, and hyperdimensional computing. As such, efficient hardware support for NN search is highly desired. In-memory computing using emerging devices offers attractive solutions for NN search. Solutions based on ternary content-addressable memories (TCAMs) offer high energy and latency improvements for NN search at the expense of accuracy. In this work, we propose a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. We evaluate the efficacy of FeFET MCAMs in the context of few-shot learning applications with different datasets. As an example, we achieve a 78.54% accuracy for a 5-way, 5-shot classification task for the mini-ImageNet dataset (only 1.5% lower than software-based implementations) when using a 3-bit MCAM for NN search. We consider the effects of FeFET threshold voltage variations on the application accuracy and analyze the area and search energy requirements of FeFET MCAMs for accurate operations. Our results indicate that MCAMs require 2× lower area and search energy than TCAMs to achieve the same accuracy. Furthermore, we experimentally demonstrate a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate the design concept. [ABSTRACT FROM AUTHOR]

This article proposes IMCRYPTO, an in-memory computing (IMC) fabric for accelerating advanced encryption standard (AES) encryption and decryption. IMCRYPTO employs a unified structure to implement encryption and decryption in a single-hardware architecture with combined (Inv)SubBytes and (Inv)MixColumns steps. Because of this step combination and the high parallelism achieved by multiple units of random access memory (RAM) and random access/content addressable memory (RA/CAM) arrays, IMCRYPTO achieves high-throughput encryption and decryption without sacrificing area and power consumption. In addition, due to the integration of an RISC-V core, IMCRYPTO offers programmability and flexibility. IMCRYPTO improves the throughput per area by a minimum (maximum) of $3.3\times $ ($223.1\times $) compared to previous ASICs/IMC architectures for AES-128 encryption. Projections show added benefit from emerging technologies of up to $5.3\times $ to the area–delay–power product of IMCRYPTO. [ABSTRACT FROM AUTHOR]

Transformer networks have outperformed recurrent and convolutional neural networks in terms of accuracy in various sequential tasks. However, memory and compute bottlenecks prevent transformer networks from scaling to long sequences due to their high execution time and energy consumption. Different neural attention mechanisms have been proposed to lower computational load but still suffer from the memory bandwidth bottleneck. In-memory processing can help alleviate memory bottlenecks by reducing the transfer overhead between the memory and compute units, thus allowing transformer networks to scale to longer sequences. We propose an in-memory transformer network accelerator (iMTransformer) that uses a combination of crossbars and contentaddressable memories to accelerate transformer networks. We accelerate transformer networks by (1) computing in-memory, thus minimizing the memory transfer overhead, (2) caching reusable parameters to reduce the number of operations, and (3) exploiting the available parallelism in the attention mechanism computation. To reduce energy consumption, the following techniques are introduced: (1) a configurable attention selector is used to choose different sparse attention patterns, (2) a contentaddressable memory aided locality sensitive hashing helps to filter the number of sequence elements by their importance, and (3) FeFET-based crossbars are used to store projection weights while CMOS-based crossbars are used as an attentional cache to store attention scores for later reuse. Using a CMOS-FeFET hybrid iMTransformer introduced a significant energy improvement compared to the CMOS-only iMTransformer. The CMOS-FeFET hybrid iMTransformer achieved an 8.96× delay improvement and 12.57× energy improvement for the Vanilla transformers compared to the GPU baseline at a sequence length of 512. Implementing BERT using CMOS-FeFET hybrid iMTransformer achieves 13.71× delay improvement and 8.95× delay improvement compared to the GPU baseline at sequence length of 512. The hybrid iMTransformer also achieves a throughput of 2.23 K samples/sec and 124.8 samples/s/W using the MLPerf benchmark using BERT-large and SQuAD 1.1 dataset, an 11× speedup and 7.92× energy improvement compared to the GPU baseline. [ABSTRACT FROM AUTHOR]

In this paper, we show that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits. Exemplarily, a 1-bit full adder circuit using a novel 5-input majority gate based on TLGs is experimentally demonstrated. The theory of pNML and its extension by TLGs is introduced, illustrating the great benefit of pNML. Majority gates based on coupling field superposition enable weighting each input by its geometry and distance to the output. Only 5 magnets, combined in two logic gates with a footprint of 1:95 µm2 and powered by a perpendicular clocking field, are required for operation. MFM and magneto-optical measurements demonstrate the functionality of the fabricated structure. Experimental results substantiate the feasibility and the benefits of the combination of threshold logic with pNML.

Dependency of errors in nanomagnet logic datalines on the dipole coupling strength is investigated. Evolution of different types of errors at different coupling strengths is studied. Dipole coupling strength in datalines is varied by changing the inter-magnet spacing from 30nm to 10 nm and the aspect ratios of the 20-nm-thick Supermalloy (Ni79Fe16Mo5) dots from 90×60 nm² to 120×60nm². An error rate improvement up to 46% is observed for inter-magnet space reduction from 30 nm to 10nm. Error rates in datalines with larger spacing are dominated by premature switching, whereas a new type of error, due to the stronger influence of the driver magnets, dominates in datalines with tighter (sub-20-nm) spacing. For same spacing, datalines with lower aspect ratio magnets show higher error rates compared to those with higher aspect ratio. [ABSTRACT FROM AUTHOR]

Content-addressable memories (CAMs) are widely used for data-centric applications where one must search for data patterns. CMOS CAMs can incur large areas and, hence, power consumption. Nonvolatile (NV) devices, such as ferroelectric field-effect transistors (FeFETs) and resistive random access memories, have been used in the design of NV CAMs to improve both logic density and power consumption. To further improve logic density, this article proposes a compact, multistate CAM (MCAM) that can store 3 bits in a cell using just one FeFET and three FinFETs per cell. Moreover, the proposed MCAM does not require a precharging phase for search as is typical with other CAM designs, which can lead to improved performance. Simulations with experimentally calibrated 22-nm FeFET and 22-nm FinFET technology models suggest that the proposed 3T1Fe-MCAM can perform up to 7.1× faster search operations with up to 28.8× lower area–energy–delay product compared with state-of-the-art ternary/analog CAM designs. To show that the proposed MCAM array can accurately detect all worst case matches/mismatches, we design an MCAM array with 11 cells per row (to represent a 32-bit number). We also study how the nonidealities related to programming/search voltages impact performance metrics and show that the proposed MCAM can tolerate up to 15-mV noise during programming and up to 20-mV noise on search voltages even in a worst case match/mismatch. [ABSTRACT FROM AUTHOR]

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory processing (NMP) and computing-in-memory (CiM)—paradigms where computation is done within the memory boundaries—represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications, such as HE. This article introduces CiM-HE, a CiM architecture that can support operations for the Brakerski/Fan–Vercauteren (B/FV) scheme, a somewhat HE scheme for general computation. CiM-HE hardware consists of customized peripherals, such as sense amplifiers, adders, bit shifters, and sequencing circuits. The peripherals are based on CMOS technology and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against: 1) two optimized CPU HE implementations and 2) a field-programmable gate array (FPGA)-based HE accelerator implementation. Compared with a CPU solution, CiM-HE obtains speedups between $4.6\times $ and $9.1\times $ and energy savings between $266.4\times $ and $532.8\times $ for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference, are up to $1.1\times $ , $7.7\times $ , $7.1\times $ , and $7.5\times $ faster (and $301.1\times $ , $404.6\times $ , $532.3\times $ , and $532.8\times $ more energy efficient). Compared with CPU-based HE in previous work, CiM-HE obtains $14.3\times $ speedup and $> 2600\times $ energy savings. Finally, our design offers $2.2\times $ speedup with $88.1\times $ energy savings compared with a state-of-the-art FPGA-based accelerator. [ABSTRACT FROM AUTHOR]

Brain-inspired hyperdimensional (HD) computing emulates cognitive tasks by computing with long binary vectors—also know as hypervectors—as opposed to computing with numbers. However, we observed that in order to provide acceptable classification accuracy on practical applications, HD algorithms need to be trained and tested on nonbinary hypervectors. In this article, we propose SearcHD, a fully binarized HD computing algorithm with a fully binary training. SearcHD maps every data points to a high-dimensional space with binary elements. Instead of training an HD model with nonbinary elements, SearcHD implements a full binary training method which generates multiple binary hypervectors for each class. We also use the analog characteristic of nonvolatile memories (NVMs) to perform all encoding, training, and inference computations in memory. We evaluate the efficiency and accuracy of SearcHD on a wide range of classification applications. Our evaluation shows that SearcHD can provide on average 31.1 × higher energy efficiency and 12.8 × faster training as compared to the state-of-the-art HD computing algorithms. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6 ×/3.2× for analog/digital modes, respectively. In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs. [ABSTRACT FROM AUTHOR]

Ternary content addressable memories (TCAMs) represent a form of logic-in-memory and are currently widely used in routers, caches, and efficient machine learning models. From a technology prospective, researchers have begun to consider various non-volatile (NV) memory technologies to design NV TCAMs that may offer improvements with respect to figures of merit, such as energy and delay when compared to conventional CMOS designs. Among these devices, ferroelectric field effect transistors (FeFETs) stand out due to their high $ {I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio, efficient voltage-driven write mechanism, low-cost, and CMOS-compatible fabrication process. We propose a 2FeFET TCAM design based on a state-of-the-art, experimentally calibrated FeFET model. We evaluate and compare our design with other TCAMs at the cell and array levels. Our results suggest that a 2FeFET TCAM requires $3.5{\times }/3200 {\times }$ less write energy than CMOS/resistive random access memory (ReRAM) TCAMs, respectively. The cell area is 13% of that of a CMOS TCAM, and is on par with ReRAM designs. The search energy-delay-product of a 2FeFET TCAM is also $4.1 {\times }/2.8 {\times }$ less than CMOS/ReRAM TCAMs, respectively. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. This article presents the design and evaluation of an accelerator for CoNNs. The system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Specifically, we present (i) the implementation of different layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modified CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identifies what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets--MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7× improvements in energy-delay product (EDP) per digit classification for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could offer 4.3× improvements in EDP when compared to other network implementations for the CIFAR-10 dataset. [ABSTRACT FROM AUTHOR]

Among the beyond-complementary metal–oxide–semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic $I_{\text {ds}}$ - $V_{\text {gs}}$ characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine-grained logic-in-memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs), resistive random access memories (ReRAMs), ferrorelectric tunnel junctions (FTJs), etc., that afford the same circuit-level functionality. Simulation results show that FeFET-based NV TCAMs offer lower area overhead than MTJ (79%) and CMOS (42% less) equivalents, as well as better search energy-delay products (EDPs) than TCAM designs based on MTJ ($149\times $), ReRAM ($1.7\times $), and CMOS ($1.3\times $) in array evaluations. NV FeFET-based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay ($4.2\times $) and dynamic power ($2.5\times $). A case study for an FeFET-based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET-based accumulator can save area (36%) and power consumption (40%) when compared with a conventional CMOS accumulator with the same structure. [ABSTRACT FROM AUTHOR]

Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this article, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Security, for the first time, will be treated as one design metric for emerging nano-architecture. Five example circuit structures including camouflaging gates, polymorphic gates, current/voltage-based circuit protectors, and current-based XOR logic are designed to show the high efficiency of silicon nanowire FETs and graphene SymFET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of non-CMOS devices. [ABSTRACT FROM AUTHOR]

We consider the design of stochastic computing (SC) hardware based on spintronic devices. SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance. When compared to charge-based devices, spin-based devices could be lower energy, nonvolatile, etc. However, spin-based devices can be fundamentally more error prone than charge-based devices. The marriage of SC architectures and spin-based devices has the potential to produce information processing systems that are robust, low energy, and nonvolatile. In this paper, we investigate SC hardware comprised of nanomagnetic logic (NML) devices. NML is a “beyond-CMOS” technology that uses bistable magnets to store, process, and move binary information. We introduce new NML circuit structures that exploit unique features of the technology to efficiently realize hardware components required for an SC system (e.g., random number generation). We also benchmark NML-based SC circuits against other implementations, and illustrate how features that are unique to NML (e.g., inherent pipelining) can lead to improved performance. Our results indicate NML SC implementations achieve smaller area footprints with reduced energy and delay when compared to CMOS equivalents. [ABSTRACT FROM PUBLISHER]

In Nanomagnet Logic, an electronic read-out device converts magnetization to electronic signals. A giant magnetoresistance (GMR) stack, with simple deposition procedures, is a good candidate for this purpose. In this paper, the authors propose a way to pattern GMR films with the help of a CO2 snow-jet to simplify device fabrication procedures. A scanning electron microscope and a vibrating sample magnetometer were used to characterize the devices and verify the feasibility of the fabrication method. Results have shown that the CO2 snow-jet process can remove sidewalls of nanopillars that are formed after lift-off of sputtered films, and the nanopillars are uniform in shape and size. This method presents a new way to fabricate electronic readout devices for Nanomagnet Logic circuits. [ABSTRACT FROM AUTHOR]