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4 results on '"Naofumi Takagi"'

1. Level-Testability of Multi-operand Adders

Author

Naofumi Takagi and N. Kito

Subjects
Adder, Serial binary adder, Multiplier (economics), Carry-save adder, Parallel computing, Test method, Fault model, Hardware_ARITHMETICANDLOGICSTRUCTURES, Operand, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Testability, Mathematics
Abstract

Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for them. A multi-operand adder is a main part of a multiplier. 6L + 2patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the depth of the multi-operand adder. A test method of the multi-operand adder used as a partial product compressor in a multiplier is also shown. This result gives an upper bound of the number of required test patterns for a multi-operand adder in any multiplier. more...

Published
2008

2. A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching.

Author

Nobutaka Kito, Kazuyoshi Takagi, and Naofumi Takagi

Subjects
INTEGRATED circuits, ELECTRIC circuits, DIGITAL electronics, DIGITAL technology, ELECTRONIC systems
Abstract

A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown. [ABSTRACT FROM AUTHOR] more...

Published
2018
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3. Square rooting by iterative multiply-additions

Author

Naofumi Takagi, Masayuki Ito, and Shuzo Yajima

Subjects
Iterative method, Multiplicative function, MathematicsofComputing_NUMERICALANALYSIS, algorithms, multiply-addition, Computer Science Applications, Theoretical Computer Science, symbols.namesake, computer arithmetic, Square root, Methods of computing square roots, Signal Processing, symbols, square rooting, Algorithm, Newton's method, Square rooting, Information Systems, Mathematics
Abstract

A new square root algorithm which is performed through iterative multiply-additions is proposed. Although its converging ratio is linear, it is faster than widely used multiplicative methods, such as the Newton-Raphson method, for practically available ROM sizes. more...

Published
1996