Search

Modern software application development imposes standards regarding high performance, scalability, and minimal system latency. Multi-threading asynchronous programming is one of the standard solutions proposed by the industry for achieving such objectives. However, the recent introduction of the reactive programming interface in Java presents a potential alternative approach for addressing such challenges, promising performance improvements while minimizing resource utilization. The research examines the migration process from the asynchronous paradigm to the reactive paradigm, highlighting the implications, benefits, and challenges resulting from this transition. To this end, the architecture, technologies, and design of a support application are presented, outlining the practical aspects of this experimental process while closely monitoring the phased migration. The results are examined in terms of functional equivalence, testing, and comparative analysis of response times, resource utilization, and throughput, as well as the cases where the reactive paradigm proves to be a solution worth considering. Across multiple scenarios, the reactive paradigm demonstrated advantages such as up to 12% reduction in memory usage, 56% faster 90th percentile response times, and a 33% increase in throughput under high-concurrency conditions. However, the results also reveal cases, such as data-intensive scenarios, where asynchronous programming outperforms reactive approaches. Additionally, possible directions for further research and development are presented. This paper not only investigates the design and implementation process but also sets a foundation for future research and innovation in dependable systems, collaborative technologies, sustainable solutions, and distributed system architecture. [ABSTRACT FROM AUTHOR]

The numba-mpi package offers access to the Message Passing Interface (MPI) routines from Python code that uses the Numba just-in-time (JIT) compiler. As a result, high-performance and multi-threaded Python code may utilize MPI communication facilities without leaving the JIT-compiled code blocks, which is not possible with the mpi4py package, a higher-level Python interface to MPI. For debugging or code-coverage analysis purposes, numba-mpi retains full functionality of the code even if the JIT compilation is disabled. The numba-mpi API constitutes a thin wrapper around the C API of MPI and is built around Numpy arrays including handling of non-contiguous views over array slices. Project development is hosted at GitHub leveraging the mpi4py/setup-mpi workflow enabling continuous integration tests on Linux (MPICH, OpenMPI & Intel MPI), macOS (MPICH & OpenMPI) and Windows (MS MPI). The paper covers an overview of the package features, architecture and performance. As of v1.0, the following MPI routines are exposed and covered by unit tests: size/rank, [i]send/[i]recv, wait[all|any], test[all|any], allreduce, bcast, barrier, scatter/[all]gather & wtime. The package is implemented in pure Python and depends on numpy, numba and mpi4py (the latter used at initialization and as a source of utility routines only). The performance advantage of using numba-mpi compared to mpi4py is depicted with a simple example, with entirety of the code included in listings discussed in the text. Application of numba-mpi for handling domain decomposition in numerical solvers for partial differential equations is presented using two external packages that depend on numba-mpi: py-pde and PyMPDATA-MPI.

The development vector of modern central processing units, which increasingly involves using a more significant number of cores and prioritizing parallelism over the high power of a single computational unit, presents new challenges for the existing software design. This work investigates and addresses the problem of access to shared memory in multithreaded environments, such as operating systems, interactive distributed computing systems, and high-performance simulation systems. Thus, the object of study is a non-blocking approach to organizing access to memory and performing basic operations with it through non-blocking synchronization. The research methods include developing an approach to organizing access to shared memory using the doubleword compare-and-swap algorithm, followed by a theoretical and practical comparison of the resulting outcome with the standard blocking access algorithm to shared memory for different configurations of the number of threads and the number of simultaneous memory access attempts. Additionally, testing was conducted within the framework of an unnamed closed-source project by integrating the solution into it, followed by A/B testing. The results showed that using non-blocking approaches is advisable, especially in comparison with locking approaches, which demonstrated a performance degradation relative to the standard allocation algorithm by more than 300 %, while non-blocking approaches provided an improvement of 40–90 %. It was also found that using hybrid approaches to the organization of shared memory systems at the software level can lead to more stable results and mitigate application performance degradation compared to classical approaches such as buddy algorithms or free lists. Despite the results obtained, the author remains cautious about the idea of memory management and pool organization at the software level and does not recommend using specialized allocation algorithms without an urgent need to speed up memory allocation itself. The purpose of these structures is still not to improve software performance directly but to enhance and speed up access to the data stored in them. [ABSTRACT FROM AUTHOR]

Simultaneous Multi-Threading (SMT) processors provide improvement over the traditional out-of-order superscalar architecture by allowing instructions from several independent threads to execute out-of-order concurrently. Maintaining the accuracy of values read from and written to memory is a great bottleneck for processor performance, as loads must stall execution until all prior store addresses are known or risk reading invalid data. Prior research in this area has mainly focused on superscalar architecture, as such, it is only natural to extend memory dependence speculation techniques to an SMT architecture. In this paper, we allow for loads among threads to execute as soon as their addresses are resolved without checking for prior memory address conflicts. Stores also perform a check on all later loads to see if any read was too early due to an address match, if so, the processor state is recovered, and the load re-issued. This aggressive technique allows for the greatest potential instructions per clock cycle gains over predictive techniques as the pipeline is never stalled for loads. Our simulations show that an overall IPC gain up to 12% and 10% is possible for both 4-threaded and 8-threaded workloads respectively. Conversely, a maximum overall IPC loss of at least 2.3% and 2% for 4-threaded and 8-threaded workloads respectively was also observed. [ABSTRACT FROM AUTHOR]

In recent times, there has been a noticeable surge in the inclination towards the implementation of network automation solutions. This trend is driven by the objective of optimizing network availability within the context of hybrid data center networks, which are becoming increasingly prevalent. Reliability, performance, scalability, and minimal resource overhead are crucial solution design characteristics that significantly impact the decisionmaking process regarding adoption. Recent research has shown that 90% of network outages happen because of human factors and 69% of respondents manage their network with manual method. That high human error of up to 90%, occurs when configuring network devices using manual method. These problems had a negative impact on the functioning of the organization and were harmful to the user. In this research, we investigate solutions to reduce network outage that caused human error using network automation using the Python programming language and multi-threading method. This network automation will reduce configuration time, eliminate human error, and significantly increase efficiency. The aim of this research is to investigate the efficacy of network automation using Python and multi-threading to reduce network outages.The method used in this research is a parallel or multi-tread execution process method using GNS3 as network simulator. Based on experimental results, the multithread automation approach is significantly faster than both the serial automation method (67 seconds) and the manual method (248 seconds), this method requiring only 41 seconds to configure all Cisco router devices. If you're looking for speed, look no farther than the multithread automation approach, which is 6 times quicker than the manual method and 3.7 times quicker than the serial automation approach. The findings of this study have substantial and immediate implications for the ability of network engineers to speed up the configuration of networks and lower the rate of human error in doing so. [ABSTRACT FROM AUTHOR]

Modern software application development imposes standards regarding high performance, scalability, and minimal system latency. Multi-threading asynchronous programming is one of the standard solutions proposed by the industry for achieving such objectives. However, the recent introduction of the reactive programming interface in Java presents a potential alternative approach for addressing such challenges, promising performance improvements while minimizing resource utilization. The research examines the migration process from the asynchronous paradigm to the reactive paradigm, highlighting the implications, benefits, and challenges resulting from this transition. To this end, the architecture, technologies, and design of a support application are presented, outlining the practical aspects of this experimental process while closely monitoring the phased migration. The results are examined in terms of functional equivalence, testing, and comparative analysis of response times, resource utilization, and throughput, as well as the cases where the reactive paradigm proves to be a solution worth considering. Across multiple scenarios, the reactive paradigm demonstrated advantages such as up to 12% reduction in memory usage, 56% faster 90th percentile response times, and a 33% increase in throughput under high-concurrency conditions. However, the results also reveal cases, such as data-intensive scenarios, where asynchronous programming outperforms reactive approaches. Additionally, possible directions for further research and development are presented. This paper not only investigates the design and implementation process but also sets a foundation for future research and innovation in dependable systems, collaborative technologies, sustainable solutions, and distributed system architecture.

Cryptocurrency markets exhibit high volatility, necessitating accurate forecasting methods for effective decision-making. This paper presents an innovative approach that integrates web scraping from cryptocurrency websites with various deep-learning networks to predict cryptocurrency values for the following day. Our web scraping technique integrated with concept like multi-threading focuses exclusively on cryptocurrency websites, extracting essential data such as live price records making use of crucial computer technology concepts like multi-threading. Combined with a suite of deep learning models including LSTM, GRU, and XgBoost, this data facilitates the modelling of temporal dependencies crucial for understanding cryptocurrency price dynamics. Through empirical evaluation, we determine the model that outperforms others and integrate it into a dashboard for real-time prediction. By leveraging real-time insights from web scraping, our model aims to enhance prediction accuracy. This research contributes to the advancement of predictive analytics in cryptocurrency trading, providing actionable insights for investors and analysts amidst fluctuating market conditions.

High performance computing (HPC) clusters are increasingly handling workloads where working data sets cannot be easily partitioned or are too large to fit into local node memory. In order to enable HPC workloads to access memory external to the node, HPE has defined a programming API (OpenFAM) for developing applications that use large‐scale disaggregated memory. In this paper we describe an open‐source reference implementation of OpenFAM that can be used on scale‐up machines, traditional HPC clusters, as well as emerging disaggregated memory architectures. We demonstrate the efficiency of the implementation using micro‐benchmarks on InfiniBand and Slingshot‐based clusters. [ABSTRACT FROM AUTHOR]

The rapid development of information technology has made the amount of information in massive texts far exceed human intuitive cognition, and dependency parsing can effectively deal with information overload. In the background of domain specialization, the migration and application of syntactic treebanks and the speed improvement in syntactic analysis models become the key to the efficiency of syntactic analysis. To realize domain migration of syntactic tree library and improve the speed of text parsing, this paper proposes a novel approach—the Double-Array Trie and Multi-threading (DAT-MT) accelerated graph fusion dependency parsing model. It effectively combines the specialized syntactic features from small-scale professional field corpus with the generalized syntactic features from large-scale news corpus, which improves the accuracy of syntactic relation recognition. Aiming at the problem of high space and time complexity brought by the graph fusion model, the DAT-MT method is proposed. It realizes the rapid mapping of massive Chinese character features to the model's prior parameters and the parallel processing of calculation, thereby improving the parsing speed. The experimental results show that the unlabeled attachment score (UAS) and the labeled attachment score (LAS) of the model are improved by 13.34% and 14.82% compared with the model with only the professional field corpus and improved by 3.14% and 3.40% compared with the model only with news corpus; both indicators are better than DDParser and LTP 4 methods based on deep learning. Additionally, the method in this paper achieves a speedup of about 3.7 times compared to the method with a red-black tree index and a single thread. Efficient and accurate syntactic analysis methods will benefit the real-time processing of massive texts in professional fields, such as multi-dimensional semantic correlation, professional feature extraction, and domain knowledge graph construction. [ABSTRACT FROM AUTHOR]

In this work, we have prepared and analyzed three case studies comparing CPU and GPGPU calculations. After briefly introducing the topic of parallel programming by means of contemporary CPU and GPGPU technologies, we provide an overview of selected existing works closely related to the topic of the paper. For each of the case studies, a set of programs has been implemented using the following technologies: pure CPU, CPU SIMD, CPU multi-threaded, CPU multi-threaded with SIMD instructions, and GPU - Cuda. We also illustrate the basic idea of the operation of selected algorithms using code snippets. Subsequently, the particular implementations are compared, and obtained results are evaluated and discussed.

Nowadays, convolutional neural networks are among the most widely used types of deep learning networks thanks to their usefulness in many application domains. There are many efforts to find methods to increase their training and inference performance and efficiency. One of the most widely used technique to implement convolution consists of flattening tensors into 2D matrices and carrying out the operation through a matrix-matrix multiplication routine, which has highly optimized implementations in high-performance libraries. However, this kind of approach uses extra time and memory to transform and store the tensors involved. For this reason, direct convolution is becoming increasingly popular. Direct convolution can be implemented as a series of nested loops iterating over tensor dimensions and it does not require extra memory. In this work, we evaluate on various multi-core CPUs the performance and scalability effects deriving from different parallelization strategies, loop organizations, and SIMD-vectorization approaches with different compilers in relation with architectural aspects. We discuss each parameter thoroughly and distill our findings in a set of heuristics that can be used to quickly achieve a high-performance implementation in accordance to the underlying hardware and the characteristics of the convolutional layer at hand. By adopting a per-layer approach, we increase performance up to 60-70% compared to a static implementation for all the layers. Moreover, our results are comparable, or even better (up to $1.67\times $ speedup) than matrix-matrix multiplication-based convolution in a multi-core system.

Abstract This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics.

In fake news detection, intelligent optimization seems to be a more effective and explainable solution methodology than the black-box methods that have been extensively used in the literature. This study takes the optimization-based method one step further and proposes a novel, multi-thread hybrid metaheuristic approach for fake news detection in social media. The most innovative feature of the proposed method is that it uses a supervisor thread mechanism, which simultaneously monitors and improves the performance and search patterns of metaheuristic algorithms running parallel. With the supervisor thread mechanism, it is possible to analyse different key attribute combinations in the search space. In addition, this study develops a software framework that allows this model to be implemented easily. It tests the performance of the proposed model on three different data sets, respectively containing news about Covid-19, the Syrian War, and daily politics. The proposed method is evaluated in comparison to the results of fifteen different well-known deep models and classification algorithms. Experimental results prove the success of the proposed model and that it can produce competitive results. [ABSTRACT FROM AUTHOR]

In detection-free tracking, after users freely designate the location of the object to be tracked in the first frame of the video sequence, the location of the object is continuously found in the following video frame sequence. Recently, technologies using a Siamese network and transformer based on DNN modules have been evaluated as very excellent in terms of tracking accuracy. The high computational complexity due to the usage of the DNN module is not a preferred feature in terms of execution speed, and when tracking two or more objects, a bottleneck effect occurs in the DNN accelerator such as the GPU, which inevitably results in a larger delay. To address this problem, we propose a tracker scheduling framework. First, the computation structures of representative trackers are analyzed, and the scheduling unit suitable for the execution characteristics of each tracker is derived. Based on this analysis, the decomposed workloads of trackers are multi-threaded under the control of the scheduling framework. CPU-side multi-threading leads the GPU to a work-conserving state while enabling parallel processing as much as possible even within a single GPU depending on the resource availability of the internal hardware. The proposed framework is a general-purpose system-level software solution that can be applied not only to GPUs but also to other hardware accelerators. As a result of confirmation through various experiments, when tracking two objects, the execution speed was improved by up to 55% while maintaining almost the same accuracy as the existing method. [ABSTRACT FROM AUTHOR]

With the rapid development of mobile internet, Android applications have become an indispensable part of people's daily lives. However, as the functionality of applications continues to increase, complexity also rises, making it one of the major challenges to efficiently and stably run applications with limited system resources. Multi-threading and concurrency handling techniques provide effective means to address this issue. This paper first analyzes the current status and challenges of applying multi-threading and concurrency handling techniques in Android application development, proposes targeted performance optimization improvements, validates their effectiveness through experiments, and finally summarizes the research results and looks ahead to future research directions.

This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]

In high-performance computing, selecting the appropriate thread count has a significant impact on execution time and energy consumption. On multi-core processor systems, it is widely believed that for maximal speedup, the total number of threads should match the number of cores. Thread migration rate, cache miss rate, thread synchronisation, and context switching rate are all impacted by changes in thread count at the hardware and OS levels. As a result, it is extremely difficult to analyse these factors for relatively complex multi-threaded programs and determine the optimal number of threads. The method put forward in this study is an enhancement of the conventional Manta-Ray Foraging Optimization, a bio-inspired approach that has been applied to a number of numerical engineering problems. The proposed approach makes use of three foraging steps: chain, cyclone, and somersault. Using the well-known benchmark suite PARSEC (The Princeton Application Repository for Shared-Memory Computers), the suggested work is simulated on an NVIDIA-DGX Intel Xeon-E5 2698-v4 processor. The findings demonstrate that the new modified AMRFO-based prediction model can choose the appropriate number of threads with fairly minimal overheads when compared to the current method. [ABSTRACT FROM AUTHOR]

As technology scales, transistors become smaller and aggressive power optimization techniques combined with high operation frequencies and performance-enhancing microarchitectural techniques are employed to achieve increasingly higher performance and power efficiencies. Unfortunately, these developments make the modern systems more vulnerable to soft errors, which are becoming a critical issues in both hardware and software domains. Motivated by this observation, in this work, we propose, implement, and evaluate two error propagation metrics in order to characterize error propagation at both software and hardware levels. The first metric aims to measure error propagation on program data structures, whereas the second one measures the fraction of corrupted locations in the cache memory structure for a given period of time. We evaluate our proposed metrics by performing an empirical study of two application programs using both single-threaded and multi-threaded executions, and varying various experimental parameters such as thread count, error rate, location of errors, and architectural parameters. Our extensive experimental analysis reveals that error propagation over program data structures is highly dependent on application behavior.Further, depending on the cache parameters used, propagation of errors on cache can exhibit different patterns. This paper also discusses how our observed error propagation trends in program data structures and data caches are correlated with each other, focusing in particular on the differences in error propagation speeds in application data structures and data caches. [ABSTRACT FROM AUTHOR]

The numerical simulation of dendritic crystal growth with melt convection in complex domains is of great significance in academic research and industrial application. However, the processing of complex boundaries, huge computational costs of three-dimensional problems and strong nonlinear coupling of multiple equations make the numerical simulation of dendritic crystal growth face great challenges. In this study, a new dendritic crystal growth phase field model with melt convection in complex domains is firstly established. The new model avoids the difficulty of dealing with complex boundaries and can be computed on the rectangle or parallelepiped. The modeling process adopts the idea of the multi-component Allen–Cahn equation modeling idea, weight factor and Lagrange multiplier. Secondly, for the efficient computation, a second-order dimension splitting numerical scheme is developed for the new model. It decomposes the high-dimensional problem into a series of one-dimensional problems which can be computed by multi-threading. Finally, to achieve decoupling, the nonlinear and coupled terms are explicitly computed, and stabilization terms are added to enhance the long-time computational stability. The accuracy and efficiency of the dimension splitting method are verified by numerical experiments. The numerical simulations of fourfold, fivefold and sixfold anisotropic single dendritic crystal growth and multiple dendritic crystal growth show that complex domains and melt convection greatly affect the normal growth pattern of dendritic crystal growth. In addition, the numerical experiments also show that when the dendritic crystal growth rate is slow, the melt convection can promote the growth rate under the same conditions. • A new dendritic crystal growth model with melt convection in complex domains is established for multi-threading simulation. • A dimension splitting scheme is proposed for the new model which can be computed by multi-threading. • A large number of dendritic crystal growth in complex domains is numerically simulated. [ABSTRACT FROM AUTHOR]

The evolution of simulation and implementation of P systems has been intense since the theoretical model of computation was created. In the field of software simulation of P systems, the proposals made so far have taken advantage mainly of the parallelism of GPUs, but not of the parallelism of existing multi-core processors. This paper proposes a new model for simulating P systems using a multi-threaded approach in a multi-core processor. This simulation approach establishes a new paradigm that is entirely in line with the philosophy of P-systems: since objects must react in parallel, asynchronously and autonomously with other objects, simulation using multiple synchronized threads completely mimics the behavior of objects within a membrane. This proposal has been implemented and tested using a simulator programmed in C#, and its correct operation has been tested for confluent and non-confluent systems. The experimental results confirm that the simulator scales well with the number of hardware threads of a multiprocessor. The obtained results show that the new model is correct and that it can be extended to other more complex types of P systems, in order to discover which are the limit of this multi-threaded approach when running it in multi-core processors. • A pioneering approach for membrane simulation based on CPU multi-threading. • The approach can be straightforwardly used to simulate generic transitive P systems. • A multi-threaded implementation of the P system simulator has been tested. • Performance speedup results directly proportional to the number of hardware threads. [ABSTRACT FROM AUTHOR]

Scalability is one of the most important quality attribute of softwareintensive systems, because it maintains an effective performance parallel to the large fluctuating and sometimes unpredictable workload. In order to achieve scalability, thread pool system (TPS) (which is also known as executor service) has been used extensively as a middleware service in software-intensive systems. TPS optimization is a challenging problem that determines the optimal size of thread pool dynamically on runtime. In case of distributed-TPS (DTPS), another issue is the load balancing b/w available set of TPSs running at backend servers. Existing DTPSs are overloaded either due to an inappropriate TPS optimization strategy at backend servers or improper load balancing scheme that cannot quickly recover an overload. Consequently, the performance of software-intensive system is suffered. Thus, in this paper, we propose a new DTPS that follows the collaborative round robin load balancing that has the effect of a double-edge sword. On the one hand, it effectively performs the load balancing (in case of overload situation) among available TPSs by a fast overload recovery procedure that decelerates the load on the overloaded TPSs up to their capacities and shifts the remaining load towards other gracefully running TPSs. And on the other hand, its robust load deceleration technique which is applied to an overloaded TPS sets an appropriate upper bound of thread pool size, because the pool size in each TPS is kept equal to the request rate on it, hence dynamically optimizes TPS. We evaluated the results of the proposed system against state of the art DTPSs by a clientserver based simulator and found that our system outperformed by sustaining smaller response times. [ABSTRACT FROM AUTHOR]

Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively hides the memory access latencies for multi-threaded graph workloads provided that sufficient threads are supported in hardware. Unfortunately, providing a sufficiently large number of physical threads incurs an unjustifiably high hardware cost for commodity SMT processors which typically implement only two physical hardware threads. Ideally, we would like to achieve aggressive-SMT performance when running graph workloads on modest commodity processors. In this paper, we propose Virtualized Multi-Threading (VMT), a low-overhead multi-threading paradigm for accelerating graph workloads on commodity processors. Unlike prior multi-threading paradigms, VMT virtualizes both the physical hardware threads and the architecture state: VMT maps a large number of logical software threads to a small number of physical hardware threads, while maintaining the architecture state of the logical threads in the processor's cache hierarchy. Implemented on top of a quad-core 2-way SMT processor, VMT achieves an average speedup of 1.74× for a set of representative graph workloads, while incurring minimal hardware cost (195 bytes per core to support up to 32 logical threads). VMT's low hardware cost paves the way for implementation in commodity processors. [ABSTRACT FROM AUTHOR]

Mining frequent itemsets is an area of data mining that has beguiled several researchers in recent years. Varied data structures such as Nodesets, DiffNodesets, NegNodesets, N-lists, and Diffsets are among a few that were employed to extract frequent items. However, most of these approaches fell short either in respect of run time or memory. Hybrid frameworks were formulated to repress these issues that encompass the deployment of two or more data structures to facilitate effective mining of frequent itemsets. Such an approach aims to exploit the advantages of either of the data structures while mitigating the problems of relying on either of them alone. However, limited efforts have been made to reinforce the efficiency of such frameworks. To address these issues this paper proposes a novel multithreaded hybrid framework comprising of NegNodesets and N-list structure that uses the multicore feature of today's processors. While NegNodesets offer a concise representation of itemsets, N-lists rely on List intersection thereby speeding up the mining process. To optimize the extraction of frequent items a hash-based algorithm has been designed here to extract the resultant set of frequent items which further enhances the novelty of the framework. [ABSTRACT FROM AUTHOR]

The internet of things (IoT) concept has been extremely investigated in many modern smart applications, which enable a set of sensors to either process the collected data locally or send them to the cloud for remote processing. Unfortunately, cloud datacenters are located far away from IoT devices, and consequently, the transmission of IoT data may be delayed. In this paper, we investigate fog computing, which is a new paradigm that overcomes many issues of cloud computing. More importantly, dynamic task offloading in fog computing is a challenging problem that requires an optimal decision for processing the tasks that are generated in each time slot. Thus, exact optimization methods based on Lyapunov function have been widely used for solving dynamic offloading which represents an NP hard problem. To overcome the scalability issue of exact optimization techniques, we have explored famous population based meta-heuristics for optimizing the offloading process of a set of dynamic tasks using Orthogonal Frequency Division Multiplexing (OFDM) communication. Hence, a parallel multi-threading framework is proposed for generating the optimal offloading solution while selecting the best sub-carrier for each offloaded task. More importantly, our contribution associates a thread for each IoT device and generates a population of random solutions. Next, each population is updated and evaluated according to the proposed fitness function that considers a tradeoff between the delay and energy consumption. Upon the arrival of new tasks at each time slot, an evaluation is performed for maintaining some individuals of the previous population while generating new individuals based on some criteria. Our results have been compared to the results achieved using Lyapunov optimization. They demonstrate the convergence of the fitness function, the scalability of the parallel Particle Swarm Optimization (PSO) approach, and the performance in terms of the offline error and the execution cost. [ABSTRACT FROM AUTHOR]

Graph analytics are an emerging class of irregular applications. Operating on very large datasets, they present unique behaviors, such as fine-grained, unpredictable memory accesses, and highly unbalanced task level parallelism, that make existing high-performance general-purpose processors or accelerators (e.g., GPUs) suboptimal. To address these issues, research and industry are developing a variety of custom accelerator designs for this application area, including solutions based on reconfigurable devices (Field Programmable Gate Arrays). These new approaches often employ High-Level Synthesis (HLS) to Speed up the development of the accelerators. In this paper, we propose a novel architecture template for the automatic generation of accelerators for graph analytics and irregular applications. The architecture template includes a dynamic task scheduling mechanism, a parallel array of accelerators that enables supporting task-level parallelism with context switching, and a related multi-channel memory interface that decouples communication from computation and provides support for fine-grained atomic memory operations. We discuss the integration of the architectural template in an HLS flow, presenting the necessary modifications to enable automatic generation of the custom architectures starting from OpenMP annotated code. We evaluate our approach first by synthesizing and exploring triangle counting, a common graph algorithm, and then by synthesizing custom designs for a set of graph database benchmark queries, representing series of graph pattern matching routines. We compare the synthesized accelerators with previous state-of-the-art methodologies for the synthesis of parallel architectures, showing that the proposed approach allows reducing resource usage by optimizing the number of accelerators replicas without any performance penalty. [ABSTRACT FROM AUTHOR]

The last decade witnessed rapid increase in multimedia and other applications that require transmitting and protecting huge amount of data streams simultaneously. For such applications, a high-performance cryptosystem is compulsory to provide necessary security services. Elliptic curve cryptosystem (ECC) has been introduced as a considerable option. However, the usual sequential implementation of ECC and the standard elliptic curve (EC) form cannot achieve required performance level. Moreover, the widely used Hardware implementation of ECC is costly option and may be not affordable. This research aims to develop a high-performance parallel software implementation for ECC. To achieve this, many experiments were performed to examine several factors affecting ECC performance including the projective coordinates, the scalar multiplication algorithm, the elliptic curve (EC) form, and the parallel implementation. The ECC performance was analyzed using the different factors to tune-up them and select the best choices to increase the speed of the cryptosystem. Experimental results illustrated that parallel Montgomery ECC implementation using homogenous projection achieves the highest performance level, since it scored the shortest time delay for ECC computations. In addition, results showed that NAF algorithm consumes less time to perform encryption and scalar multiplication operations in comparison with Montgomery ladder and binary methods. Java multi-threading technique was adopted to implement ECC computations in parallel. The proposed multithreaded Montgomery ECC implementation significantly improves the performance level compared to previously presented parallel and sequential implementations. [ABSTRACT FROM AUTHOR]

The multiplication of computing cores in modern processor units permits revisiting the design of classical algorithms to improve computational performance in complex application domains. Artificial Intelligence planning is one of those applications where large search spaces require intelligent and more exhaustive search control. In this paper, parallel planning algorithms, derived from best-first search, are proposed for shared memory architectures. The parallel algorithms, based on the asynchronous work pool paradigm, maintain good thread occupancy in multi-core CPUs. All algorithms use one ordered global list of states stored in shared memory from where they select nodes for expansion. A parallel best-first search algorithm that develops new states with depth equal to one is proposed first. Then, we propose an extension of this parallel algorithm that features a diversification strategy in order to escape local minima. We study and analyse a set of computational experiments for problems that come from the International Planning Competition and real-world industry applications. The empirical evaluation shows that the parallel algorithms solve most of the domains efficiently without incurring higher solutions costs. In those problems with partial results, we highlight the potential shortcomings of the proposed approaches for promising future directions. [ABSTRACT FROM AUTHOR]

This letter investigates parallelism approaches for equation and Jacobian evaluations in large-scale power flow calculation. Two levels of parallelism are proposed and analyzed: inter-model parallelism, which evaluates models in parallel, and intra-model parallelism, which evaluates calculations within each model in parallel. Parallelism techniques such as multi-threading and single instruction multiple data (SIMD) vectorization are discussed, implemented, and benchmarked as six calculation workflows. Case studies on the 70 000-bus synthetic grid show that equation evaluations can be accelerated by ten times, and the overall Newton power flow advances the state of the art by 20%. [ABSTRACT FROM AUTHOR]

Comprehending existing multi-threaded applications effectively is a challenge without proper assistance. Research has been proposed to mine programs to extract aspects of high-level design but not much to reverse-engineer the concurrent design from multi-threaded applications. To address the same, we develop a generic mathematical model to interpret run-time non-deterministic events and encode functional as well as thread-specific behaviour in form of quantifiable features, which can be fitted into a standard solver for automated inference of design aspects from multi-threaded applications. We build a tool Dcube based on the mathematical model and use various classifiers of a machine learning framework to infer design aspects related to concurrency and resource management. We collect a dataset of 480 projects from Github, CodeProject and Stack Overflow and 3 benchmark suites—CDAC Pthreads, Open POSIX Test Suites and PARSEC 3.0 and achieve an accuracy score of around 93.71% for all the design choices. [ABSTRACT FROM AUTHOR]

We investigated improvements to further speed up the multi-threaded scaling of the distributed hydrological model wflow_sbm. To gain insight in the speed improvements for operational applications, we connected the improved code to ECMWF's Fields Database to allow for on-the-fly pre-processing of the forcing, which accelerated the entire forecasting chain. In the original wflow_sbm implementation, run times increased when more than eight threads were used due to Julia's native threading overhead. Now, run times are 2 to 11 times faster, depending on the chosen routing scheme, number of threads and catchment size. We show the advantages of the improvements in a test setup where ECMWF forecasts and 35 years of ERA5 reanalysis data were used to force wflow_sbm models at 1x1 km spatial resolution for Europe. The attained speedup allows for using distributed hydrological models in large-scale hydrological forecasting and climate-change applications, which is currently often limited to lumped models. • Improved multi-threaded scaling of the distributed hydrological model wflow_sbm. • Two to eleven times faster run times on high-performance computing clusters. • Distributed hydrological model application for large-scale hydrological forecasting. [ABSTRACT FROM AUTHOR]

The main goal of oil reservoir management is to provide more efficient, price-effective and environmentally more secure oil production. Oil production management includes an accurate characterization of the reservoir and strategies that involve interactions between reservoir data and human assessment. Hence, it is important to graphically visualize and handle massive data sets of oil and gas pressure / saturation levels to help decision makers in statistical analysis, history matching and recovery of hydrocarbons of the reservoir. In this article, we experimentally study the parallelization of intensive computation for a 3-D (three dimensional) oil reservoir data visualization tool. For this tool, we develop and implement a transformation and lighting model to visualize and react with the grid. Herein, we propose a hybrid (shared memory and distributed memory) parallelization technique to adapt with the data processing scalability. We tested these implementations on OpenStack Cloud Virtual Cluster. Our results indicate that although the virtual platform adds overhead for running parallel implementations, utilizing knowledge of the VM location on the compute host and network traffic among VMs to deploy the virtual environment can achieve significant performance enhancements. Hybrid parallel implementation using large data size can achieve $70\times $ speedup over serial execution without owning a costly HPC infrastructure as the conventional parallel processing deployment model.

Different machine learning and deep learning-based approaches have been proposed for designing defensive mechanisms against various phishing attacks. Recently, researchers showed that phishing attacks can be performed by employing a deep neural network-based phishing URL generating system called DeepPhish. To prevent this kind of attack, we design an ensemble machine learning-based detection system called PhishHaven to identify AI-generated as well as human-crafted phishing URLs. To the best of our knowledge, this is the first study to consider detecting phishing attacks by both AI and human attackers. PhishHaven employs lexical analysis for feature extraction. To further enhance lexical analysis, we introduce URL HTML Encoding to classify URL on-the-fly and proactively compare with some of the existing methods. We also introduce a URL Hit approach to deal with tiny URLs, which is an open problem yet to be solved. Moreover, the final classification of URLs is made on an unbiased voting mechanism in PhishHaven, which aims to avoid misclassification when the number of votes is equal. To speed up the ensemble-based machine learning models, PhishHaven employs a multi-threading approach to execute the classification in parallel, leading to real-time detection. Theoretical analysis of our solution shows that (1) it can always detect tiny URLs, and (2) it can detect future AI-generated Phishing URLs based on our selected lexical features with 100% accuracy. Through experiments, we analyze our solution with a benchmark dataset of 100,000 phishing and normal URLs. The results show that PhishHaven can achieve 98.00% accuracy, outperforming the existing lexical-based human-crafted phishing URLs detection systems.

The LHCb experiment at the Large Hadron Collider (LHC) at CERN has successfully performed a large number of physics measurements during Runs 1 and 2 of the LHC. Monte Carlo simulation is the key to the interpretation of these and future measurements. The LHCb experiment is currently undergoing a major detector upgrade for Run 3 of the LHC to process events with five times higher luminosity. New simulation software technologies have to be introduced to produce simulated data samples of sufficient size within the computing resources allocated for the next few years. Therefore, the LHCb collaboration is currently preparing an upgraded version of its Gauss simulation framework. The new version provides the LHCb specific functionality while its generic simulation infrastructure has been encapsulated in an experiment independent framework, Gaussino. The latter combines the Gaudi core software framework and the Geant4 simulation toolkit and fully exploits their multi-threading capabilities. A prototype of a fast simulation interface to the simulation toolkit is being developed as the latest addition to Gaussino to provide an extensive palette of fast simulation models, including new deep learning-based options. [ABSTRACT FROM AUTHOR]

With the rapid developments in cloud computing and mobile networks, multimedia content can be accessed conveniently. Recently, some novel intelligent caching-based approaches have been proposed to improve the memory architectures for multimedia applications. These applications often face bottleneck related challenges which result in performance degradation and service delay issues. Intelligent multimedia network applications access the shared data by using a specific network file system. This results in answering the processing related constraints on hard-drive storage and might result in bringing bottleneck issues. Therefore, to improve the performance of these multimedia network applications, we present an intelligent distributed memory caching system. We integrate the multimedia application message passing interface in a multi-threaded environment and propose an algorithm which can handle concurrent response behavior for different multimedia applications. Results demonstrate that our proposed scheme outperforms traditional approaches in terms of throughput and file read access features. [ABSTRACT FROM AUTHOR]

In this article, we present a modified version of the Firefly Algorithm implemented in a multi-threaded modelto improve the results obtained by the original algorithm significantly. This multi-threaded algorithm allowsthe threads to obtain different results by the independent execution of the heuristic method in each of them,although for keeping all the threads with significant executions, the algorithm performs some crossovertechniques, explained in detail in this article, for the threads to learn between them while maintaining itsindependence. For testing the new algorithm, we use the six benchmark functions used in the literature fortesting the original Firefly Algorithm, and to prove that the improved results are significant, we perform theWilcoxon test to the results obtained. The results obtained with this new heuristic proved to be significantlybetter while taking advantage of today’s commercial processors.

We propose two novel techniques for overcoming load-imbalance encountered when implementing so-called look-ahead mechanisms in relevant dense matrix factorizations for the solution of linear systems. Both techniques target the scenario where two thread teams are created/activated during the factorization, with each team in charge of performing an independent task/branch of execution. The first technique promotes worker sharing (WS) between the two tasks, allowing the threads of the task that completes first to be reallocated for use by the costlier task. The second technique allows a fast task to alert the slower task of completion, enforcing the early termination (ET) of the second task, and a smooth transition of the factorization procedure into the next iteration. The two mechanisms are instantiated via a new malleable thread-level implementation of the basic linear algebra subprograms, and their benefits are illustrated via an implementation of the LU factorization with partial pivoting enhanced with look-ahead. Concretely, our experimental results on an Intel-Xeon system with 12 cores show the benefits of combining WS+ET, reporting competitive performance in comparison with a task-parallel runtime-based solution.

As MOS device sizes continue shrinking, lower charges, for example those charges carried by single ionizing particles of naturally occurring radiation, are sufficient to upset the functioning of complex modern microprocessors. In order to handle these inevitable errors, designs should include fault-tolerant features so that the processors can continue to correctly perform despite the occurrence of errors. The main goal of this work is to develop architecture mechanisms to protect processors against the effect of such radiation-induced transient faults. It should first be noted that, from a program execution perspective, many faults manifest themselves as control flow errors that cause processors to violate the correct sequencing of instructions. We present here at first a basic compile-time signature assignment algorithm and describe a novel approach to improve the fault detection coverage of the basic algorithm. Moreover, to allow the processor to efficiently check the run-time sequence and detect control flow errors, we introduce an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). Second, since the very concept of simultaneous multi-threading (SMT) provides the necessary redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of an error, the rolling back of the processor state to a known safe point, and then a retry of the instructions, thereby effecting a completely error-free execution. This paper has focused on two crucial implementation issues introduced by this scheme: (1) the design trade-off between the fault detection coverage versus design costs; (2) the possible occurrence of deadlock situations.

In the preceding Part I, a combined experimental-numerical study to characterize fine spray-dried powder used in the ceramic tile pressing process was presented. In the present Part II, the algorithm proposed by (Mazhar, 2011) to solve the numerical simulation of powder dynamics through the Discrete Element Method (DEM) was extended. In this paper, the original algorithm was adapted for efficient use on multi-core CPUs and a single GPU. In both cases, history-dependent contact models were considered. The efficiency of the algorithms was compared among them and with LIGGGHTS, a reference software package for particle simulation using DEM. The results demonstrated a higher performance of the codes developed compared to LIGGGHTS, particularly in demanding scenarios with a large number of particles (more than 1 million) of small size (median diameter in volume less than 1 mm). In particular, the CPU-based algorithm was suitable for simulating the mould filling in ceramic tiles industry. Unlabelled Image • A novel GPU and CPU-based DEM algorithm is developed. • Any general-purpose contact model can be used without restrictions in the contact searching. • The developed algorithms are fairly compared with LIGGGHTS. • Developed CPU-based DEM algorithm outperforms LIGGGHTS in demanding filling scenarios. • GPU-based DEM algorithm executed on a single GPU does not enhance the CPU-based algorithm. [ABSTRACT FROM AUTHOR]

Smart Grids (SG) have smart meters and advance metering infrasturutre (AMI) which generates huge data. This data can be used for predicting energy consumption using big data analytics. A very limited work has been carried out in the literature which shows the utilization of big data in energy consumption prediction. In this paper, the proposed method is based on Genetic Algorithm - Long Short Term Memory (GA-LSTM). LSTM memorises values over an arbitrary interval that manages time series data very effictively while GA is an evolutionary process that is used for optimization. GA combines with LSTM to process hyperparameters such as hidden layers, epochs, data intervals, batchsize and activation functions. Hence, GA creates a new vector for optimum solution that provides minimum error. These methods provide the best performance when compared with existing benchmarks. Moreover, GA-LSTM is used in a multi-threaded environment which increases the speed of convergence. Here, the multi-core platform is operated for solving one-dimensional GA-based inverse scattering problems. The result shows that GA-LSTM provides better convergence as compared to random approach techniques. For validating the results, Pennsylvania-New Jersey-Maryland Interconnection (PJM) energy consumption data has been used while adopting different performance evaluation metrics. [ABSTRACT FROM AUTHOR]

The categorisation of network packets according to multiple parameters such as sender and receiver addresses is called packet classification. Packet classification lies at the core of Software‐Defined Networking (SDN)‐based network applications. Due to the increasing speed of network traffic, there is an urgent need for packet classification at higher speeds. Although it is possible to accelerate packet classification algorithms through hardware implementation, this solution imposes high costs and offers limited development capacity. On the other hand, current software methods to solve this problem are relatively slow. A practical solution to this problem is to parallelise packet classification using multi‐core processors. In this study, the Thread, parallel patterns library (PPL), open multi‐processing (OpenMP), and threading building blocks (TBB) libraries are examined and implemented to parallelise three packet classification algorithms, i.e. tuple space search, tuple pruning search, and hierarchical tree. According to the results, the type of algorithm and rulesets may influence the performance of parallelisation libraries. In general, the TBB‐based method shows the best performance among parallelisation libraries due to using a theft mechanism and can accelerate the classification process up to 8.3 times on a system with a quad‐core processor. [ABSTRACT FROM AUTHOR]

In this article, we present a modified version of the Firefly Algorithm implemented in a multi-threaded model to improve the results obtained by the original algorithm significantly. This multi-threaded algorithm allows the threads to obtain different results by the independent execution of the heuristic method in each of them, although for keeping all the threads with significant executions, the algorithm performs some crossover techniques, explained in detail in this article, for the threads to learn between them while maintaining its independence. For testing the new algorithm, we use the six benchmark functions used in the literature for testing the original Firefly Algorithm, and to prove that the improved results are significant, we perform the Wilcoxon test to the results obtained. The results obtained with this new heuristic proved to be significantly better while taking advantage of today's commercial processors. [ABSTRACT FROM AUTHOR]

The study presents a hardware‐based approach to modelling and design of time‐predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real‐time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM‐like RISC solutions and its heart, the main core, is built of 8–12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex‐7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research. [ABSTRACT FROM AUTHOR]

Nowadays, advanced smart mobile devices equipped with multi-core central processing units for handling multithreaded (MT) applications. However, existing research mainly uses single-thread (ST) computing to deal with applications, which limits the performance of mobile computing. To make full use of multi-core resources, this study proposes a fine-grained MT offloading strategy to solve the offloading problem of MT application. The strategy jointly schedules cloud computing resources, as well as local multi-core computing and communication resources. Precisely, the authors first formulate the minimum energy consumption problem for ST offloading. Then, they prove that the problem is convex and solve it by standard convex optimisation technique. Thirdly, they extend the optimisation goals from ST applications to MT applications, and design calculation rules for MT applications to reduce computing costs. Finally, based on these calculation rules and the optimal solution for ST offloading, they develop a MT offloading strategy to solve the computation offloading problem of MT applications. Simulation results show that the proposed fine-grained MT offloading strategy effectively reduces the minimum delay requirement of mobile computing. [ABSTRACT FROM AUTHOR]

Frequent dynamic memory allocations (DyMAs) can significantly hinder the scalability of parallel multi-threaded programs. As the number of threads grows, DyMAs can even become the main performance bottleneck. We introduce modern tools and methods for evaluating the impact of DyMAs and present techniques for its reduction, which include scalable heap implementations, small buffer optimization, and memory pooling. Additionally, we provide a survey of state-of-the-art implementations of these techniques and study them experimentally by using a benchmark program, server simulator software, and a real-world high-performance computing application. As a result, we show that relatively small modifications in parallel program's source code or a way of its execution may substantially reduce the runtime overhead associated with the use of dynamic data structures. [ABSTRACT FROM AUTHOR]

We investigate a parallelization strategy for dense matrix factorization (DMF) algorithms, using OpenMP, that departs from the legacy (or conventional) solution, which simply extracts concurrency from a multi-threaded version of basic linear algebra subroutines (BLAS). The proposed approach is also different from the more sophisticated runtime-based implementations, which decompose the operation into tasks and identify dependencies via directives and runtime support. Instead, our strategy attains high performance by explicitly embedding a static look-ahead technique into the DMF code, in order to overcome the performance bottleneck of the panel factorization, and realizing the trailing update via a cache-aware multi-threaded implementation of the BLAS. Although the parallel algorithms are specified with a high level of abstraction, the actual implementation can be easily derived from them, paving the road to deriving a high performance implementation of a considerable fraction of linear algebra package (LAPACK) functionality on any multicore platform with an OpenMP-like runtime. [ABSTRACT FROM AUTHOR]

A parallel Simulated Annealing algorithm with multi-threaded architecture is proposed to solve a real bi-objective maintenance scheduling problem with conflicting objectives: the minimisation of the total equipment downtime caused by maintenance jobs and the minimisation of the multi-skilled workforce requirements over the given horizon. The maintenance jobs have different priorities with some precedence relations between different skills. The total weighted flow time is used as a scheduling criterion to measure the equipment availability. The multi-threaded architecture is used to speed up a multi-objective Simulated Annealing algorithm to solve the considered problem. Multi-threading is a form of parallelism based on shared memory architecture where multiple logical processing units, so-called threads, run concurrently and communicate via shared memory. The performance of the parallel method compared to the exact method is verified using a number of test problems. The obtained results imply the high efficiency and robustness of the proposed heuristic for both solution quality and computational effort. [ABSTRACT FROM AUTHOR]

Abstract Background Recent breakthroughs in molecular biology and next generation sequencing technologies have led to the expenential growh of the sequence databases. Researchrs use BLAST for processing these sequences. However traditional software parallelization techniques (threads, message passing interface) applied in newer versios of BLAST are not adequate for processing these sequences in timely manner. Methods A new method for array job parallelization has been developed which offers O(T) theoretical speed-up in comparison to multi-threading and MPI techniques. Here T is the number of array job tasks. (The number of CPUs that will be used to complete the job equals the product of T multiplied by the number of CPUs used by a single task.) The approach is based on segmentation of both input datasets to the BLAST process, combining partial solutions published earlier (Dhanker and Gupta, Int J Comput Sci Inf Technol_5:4818-4820, 2014), (Grant et al., Bioinformatics_18:765-766, 2002), (Mathog, Bioinformatics_19:1865-1866, 2003). It is accordingly referred to as a “dual segmentation” method. In order to implement the new method, the BLAST source code was modified to allow the researcher to pass to the program the number of records (effective number of sequences) in the original database. The team also developed methods to manage and consolidate the large number of partial results that get produced. Dual segmentation allows for massive parallelization, which lifts the scaling ceiling in exciting ways. Results BLAST jobs that hitherto failed or slogged inefficiently to completion now finish with speeds that characteristically reduce wallclock time from 27 days on 40 CPUs to a single day using 4104 tasks, each task utilizing eight CPUs and taking less than 7 minutes to complete. Conclusions The massive increase in the number of tasks when running an analysis job with dual segmentation reduces the size, scope and execution time of each task. Besides significant speed of completion, additional benefits include fine-grained checkpointing and increased flexibility of job submission. “Trickling in” a swarm of individual small tasks tempers competition for CPU time in the shared HPC environment, and jobs submitted during quiet periods can complete in extraordinarily short time frames. The smaller task size also allows the use of older and less powerful hardware. The CDRH workhorse cluster was commissioned in 2010, yet its eight-core CPUs with only 24GB RAM work well in 2017 for these dual segmentation jobs. Finally, these techniques are excitingly friendly to budget conscious scientific research organizations where probabilistic algorithms such as BLAST might discourage attempts at greater certainty because single runs represent a major resource drain. If a job that used to take 24 days can now be completed in less than an hour or on a space available basis (which is the case at CDRH), repeated runs for more exhaustive analyses can be usefully contemplated.