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As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N. [ABSTRACT FROM AUTHOR]

Defects in integrated circuit (IC) packaging are inevitable. Several factors can cause defects in IC packaging such as material quality, errors in machine and human handling operations, and non-optimized processes. An automated optical inspection (AOI) is a typical method to find defects in the IC manufacturing field. Nevertheless, AOI requires human assistance in the event of uncertain defect classification. Human inspection often misses very tiny defects and is inconsistent throughout the inspection. Therefore, this study proposed a low-cost IC packaging defect classification system using edge impulse and ESP32-CAM. The method involves training a deep learning model (i.e., convolutional neural network (CNN)) using a dataset of non-defective and defective ICs on Edge Impulse. For defective ICs, the top surface of the ICs is deliberately scratched to imitate the cosmetic defects. ICs with scratch-free on their top surfaces are considered non-defective ICs. A successfully trained model using Edge Impulse is subsequently deployed on ESP32-CAM. The model is optimized to fit the limited resources of the ESP32-CAM. By using the built-in camera in ESP32-CAM, the trained model can perform a real-time image classification of non-defective/defective ICs. The proposed system achieves 86.1% prediction accuracy by using a 1,571 image dataset of defective and non-defective ICs. [ABSTRACT FROM AUTHOR]

Respiration-related disease refers to a wide range of conditions, including influenza, pneumonia, asthma, sudden infant death syndrome (SIDS) and the latest outbreak, coronavirus disease 2019 (COVID-19), and many other respiration issues. However, real-time monitoring for the detection of respiratory disorders is currently lacking and needs to be improved. Realtime respiratory measures are necessary since unsupervised treatment of respiratory problems is the main contributor to the rising death rate. Thus, this paper reviewed the classification of the respiratory signal using two different approaches for real-time monitoring applications. This research explores machine learning and deep learning approaches to forecasting respiration conditions. Every consumption of these approaches has been discussed and reviewed. In addition, the current study is reviewed to identify critical directions for developing respiration real-time applications. [ABSTRACT FROM AUTHOR]

Chipping has emerged as a significant issue in semiconductor manufacturing, particularly during the dicing process. The existing conventional single-sided wafer mounting technique does not have sufficient holding capability which contributes to instability during dicing and causes higher chipping performance. The objective of the study is to develop a novel wafer mounting technique that can hold the wafer firmly during dicing and improve the chipping performance. In the experiment, chipping and vibration performance during the dicing process on novel double-sided semi and full-sandwich wafer mounting were investigated and compared with the conventional single-sided wafer mounting technique. Chipping was measured using high power scope and ImageJ software while the vibration was initiated using the NI 9234 Sound-Vibration Module and SDT1-028K Piezoelectric film. Implementing extended surface tape coverage on double-sided UV mounting tape for the full sandwich wafer mounting technique resulted in superior wafer gripping during dicing and produced the lowest topside and backside wafer chipping performance. The novel double-sided full sandwich wafer mounting technique has demonstrated higher wafer holding capability, resulting in lower vibration during dicing and improved overall chipping performance [ABSTRACT FROM AUTHOR]

Pneumonia, asthma, sudden infant death syndrome (SIDS), and the most recent epidemic, COVID-19, are the most common lung diseases associated with respiratory difficulties. However, existing health monitoring systems use large and in-contact devices, which causes an uncomfortable experience. The difficulty in acquiring breathing signals for non-stationary individuals limits the use of ultra-wideband radar for breathing monitoring. This is due to ineffective signal clutter removal and body movement removal algorithms for collecting accurate breathing signals. This paper proposes a breathing signal analysis for non-contact physiological monitoring to improve quality of life. The radar-based sensors are used for collecting the breathing signal for each subject. The processed signal has been analyzed using continuous wavelet transform (CWT) and wavelet coherence with the Monte Carlo method. The finding shows that there is a significant difference between the three types of breathing patterns; normal, high, and slow. The findings may provide a comprehensive framework for processing and interpreting breathing signals, resulting in breakthroughs in respiratory healthcare, illness management, and overall well-being. [ABSTRACT FROM AUTHOR]

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms. [ABSTRACT FROM AUTHOR]

Breast cancer is one of the life-threatening cancer that leads to the most death due to cancer among women. Early diagnosis might help to reduce mortality. Thus, this research aims to study different approaches to the deep learning neural network model for breast cancer early detection for better prognosis. The performance of deep learning approaches such as Artificial Neural Network (ANN), Recurrent Neural Network (RNN) and Convolution Neural Network (CNN) is evaluated using the dataset from the University of Wisconsin. The findings show ANN achieved high accuracy of 99.9 % compared to others in detecting breast cancer. ANN can deliver better results with the provided dataset. However, more improvement is needed for better performance to ensure that the approach used is reliable enough for early breast cancer diagnosis. [ABSTRACT FROM AUTHOR]

As complementary metal-oxide semiconductor (CMOS) technology continues to scale down to ultra-deep submicron (UDSM) technology, the planar metal-oxide semiconductor field-effect transistor (MOSFET) structure reaches its limit. As the channel length shrinks, the gate no longer has full control over the channel which is not desirable. The subthreshold leakage from drain to source increases as the impact over the lost control of the MOS gate terminal, and further increase the total power consumption. To ensure the continuation of CMOS scaling and to overcome the aforementioned issues, the new MOS structure which is known as fin field-effect transistor (FinFET) is introduced. On the other hand, Physical Unclonable Function (PUF) is a promising hardware-fingerprinting technology that can exploit the intrinsic process variations of CMOS technology and manifest them into unique and random binary responses. These responses can be used as a cryptographic key or device specific identifier. Nevertheless, FinFET introduces an unknown impact of its process variations towards the performance of a particular PUF. In this paper, the suitability of the FinFET technology node for a PUF as a device-specific identifier or secret key is evaluated. One of the memory-PUFs, known as static random-access memory PUF (SRAM-PUF) has been used as a case study. Three different FinFET technology nodes which are 14-nm, 10-nm, and 7-nm have been evaluated. Our findings show that the uniqueness and uniformity of SRAM-PUF still hold, closely distributed at around an ideal value of 50%. The average reliability under temperature variations of -40°C to 85°C is approximately about 98%. The reliability of SRAM-PUF responses under the Vdd ramp-up time variations has no significant impact although showing declining patterns at fast ramp-up time. It can be concluded that FinFET technology shows no surprises on SRAM-PUF performances. [ABSTRACT FROM AUTHOR]

Physical Unclonable Functions (PUFs) are considered to be a promising technology that provides a hardware root-of-trust for integrated circuit (IC) applications. PUFs exploit the intrinsic process variations that map a set of challenges to a set of responses. The intrinsic process variations are caused by uncontrollable deviations in the IC manufacturing process, which are unique and random from die to die and wafer to wafer. As the PUF output is device-specific, PUFs can, therefore, be used in IC identification and authentication, and cryptographic key generation. Nevertheless, many different successful attack techniques have already revealed vulnerabilities in certain PUFs, including invasive, semi-invasive and noninvasive attacks. In this work, we survey some of the known attacks on PUFs. We also survey the countermeasures to these types of attack presented in recent literature, and finally, discuss the future challenges. Through this survey, the susceptibility of PUFs to attacks is highlighted and this information may be used to improve the quality of future PUF-based application designs. [ABSTRACT FROM AUTHOR]

Process automation is crucial to increase productivity, more efficient use of materials, better product quality, improved safety, etc. In small-medium enterprise (SME) businesses related to household retailing, one of the process automation needed is the measurement and cutting of the mat or sheet, made of rubber or polyvinyl chloride (PVC) materials. Most of the household retailers that selling the sheet, the process of measuring and cutting according to the customer’s requirements are manually performed using a measuring tape and scissors. These manual processes can cause inaccuracy in length, inefficient use of material, low productivity and reduce product quality. This paper presents a low cost and portable automatic sheet cutter using the Arduino development board, which is used to control the process of measuring and cutting the materials. The system uses a push-button where the user can set the required length and quantity of the sheet. Once the required information is set, the stepper motor rolls the sheet until the required length is satisfied. Subsequently, another stepper motor moves the cutter horizontally and cut the sheet. With the automatic sheet cutter, the material is cut with acceptable precision. The design of the automatic sheet cutter is low cost and portable which significantly suitable to be used by SME household retailers. [ABSTRACT FROM AUTHOR]

Silicon wafers have been widely used in semiconductor manufacturing, and chipping issues often highlighted during wafer dicing which affects device performance and reliability. The phenomenon of chipping has been observed to have detrimental effects on die strength, leading to the potential of crack formation. Cracks became a major concern because its sometimes undetected during testing and had been reported to cause malfunctions at user applications. This study aims to comprehensively analyze the fragile behavior of silicon concerning its chipping and flexural strength performance, providing valuable insights for engineering applications. The research employed new wafer mounting techniques, including chipping analysis, a three-point bending test and scanning electron microscopy (SEM) to reduce silicon die chipping and increase the flexural strength by evaluating the novel semi and full sandwich wafer mounting techniques. The study demonstrated that the implementation of novel full sandwich mounting technique had improved significantly the silicon die chipping and flexural die performance among all the wafer mounting techniques. [ABSTRACT FROM AUTHOR]