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In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL. Index Terms--All-digital phase-locked loop (PLL), bilinear transform, digital loop filter, digitally controlled oscillator.

This paper presents an approach to reduce substrate cross-talk noise between noisy and sensitive circuitry in mixed-signal integrated circuits at different stages of design and layout development. Silencer! a new, fully automated, schematic-driven substrate noise coupling analysis tool is introduced to accomplish this task. The tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. Two different methods, fast scalable macro-models and a boundary element solver are integrated into Silencer!. These methods allow extractions of a substrate network from geometric layout information. Simulation results obtained with Silencer! are accurate to within 10% of measured integrated circuits. Index Terms--Coupling noise, integrated circuit noise, mixed-signal noise, noise analysis tool, noise minimization, pre-/post-layout analysis, substrate noise, substrate noise analysis, supply noise.

An n-contact to p-contact model is proposed for analyzing substrate noise coupling in mixed-signal integrated circuits. The self-coupling parameters for n-p structures are similar to those for p-p structures and the cross-coupling parameters of the n-p structures are similar to those of the p-p structures at large separations.

A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior. Index Terms--Circuit simulation, coupled circuit and device simulation, electrostatic/mechanical simulator, microelectromechanical systems (MEMS) capacitor, microelectromechanical systems voltage-controlled oscillator (MEMS VCO), noise simulation, phase noise, radio frequency voltage-controlled oscillator (RF VCO).

In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE. Index Terms--Impulse invariance, jitter, loop delay., phase-locked loop (PLL), phase noise, state space, z-domain.

In this paper, a new formulation for the extraction of substrate parasitics is derived that can account for the nonuniform current distribution on contacts without contact subdivision. This method is orders of magnitude faster than the original Green's function method. The speedup is achieved by a significantly reduced matrix size combined with the application of the discrete sine transform. The method is accurate, and is well suited for large problems. Index Terms--Green's function, noise modeling, substrate coupling, substrate noise, substrate parasitic extraction.

In this paper, a new nonlinear finite element model is presented for the analysis of piezoelectric laminates at large deflections. The element is an eight-node element with 5 mechanical degrees of freedom at each node, and the potential difference across the piezoelectric layer is introduced as an additional electrical degree of freedom on an element level. Application of this model to a clamped square piezoelectric laminate shows the strong nonlinear relationship between the terminal voltage and deflection observed experimentally. Further more, the numerical results also show that the electrode size is an important design parameter in maximizing the power output when the piezoelectric laminates are used as power generators. [970] Index Terms--MEMS devices, micropower generation, non-linear FEM, piezoelectric devices, piezoelectric laminate analysis.

In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta–sigma analog-to-digital converter (ADC) structure is presented. This architecture does not require any operational transconductance amplifier (OTA)-based analog integrators or power-hungry linearization methods. The first stage is a closed-loop multi-phase VCO-based voltage-to-phase (V-to-P) converter, and the second stage is an open-loop multi-phase VCO-based voltage-to-frequency (V-to-F) converter. Using the proposed technique, the phase quantization error of the first stage is extracted as a pulse signal and then fed to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power-hungry linearization methods. The prototype achieves second-order noise shaping with a DR/SFDR/SNR/SNDR of 82.7/88.7/80.3/79.7 dB for an input signal BW of 2 MHz. The fabricated design consumes 1.248 mW from a 0.9-V supply. [ABSTRACT FROM AUTHOR]

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7-MHz bandwidth and a Walden figure-of-merit of 341 fJ/conversion. [ABSTRACT FROM AUTHOR]

A two-stage continuous-time $\Delta \Sigma $ modulator with voltage-controlled oscillator based quantizer (VCOQ) is presented. The presented modulator suppresses the VCOQ voltage-to-frequency nonlinearity through dual path cancellation to achieve high linearity. As an added advantage, this architecture exhibits strong immunity to the first stage quantization error leakage to the output due to gain mismatches between the two stages. Fabricated in a 65 nm CMOS technology, the prototype modulator operates at 1.5 GS/s and achieves 76.1 dB SNR, 73.5 dB SNDR, 88 dB SFDR, and 76.1 dB dynamic range (DR) in 50 MHz bandwidth. This prototype demonstrates robust performance with less than 1.5 dB variation in SNDR for ±10% gain mismatch between the two stages. Also, the SNDR variation remains within 1 dB for a temperature variation of 0°C–80°C. The modulator consumes 51.8 mW of power leading to a Walden FoM of 134 fJ/conv-step. [ABSTRACT FROM AUTHOR]

A power generation method based fast start‐up analysis of resonator based oscillators is presented. The power generation analysis uses a small‐signal two‐port based approach and is design oriented. The analysis has been validated with detailed circuit level simulations. Several metal–oxide–semiconductor field‐effect transistor oscillator architectures have been analysed and the start‐up times compared using this analysis. [ABSTRACT FROM AUTHOR]

A new enhanced swing class-D VCO which operates from a supply voltage as low as 300 mV is presented. The architectural advantages are described along with an analysis for the oscillation frequency. Prototype differential and quadrature variants of the proposed VCO have been implemented in a 65 nm RF CMOS process with a 5 GHz VCO oscillation frequency. At a 350 mV supply, the measured phase noise performance for the quadrature VCO with a 5% tuning range is -137.1 dBc/Hz at 3 MHz offset with a power dissipation of 2.1 mW from a 0.35 V supply. The highest resulting figure-of-merit (FoM) is 198.3 dBc/Hz. [ABSTRACT FROM PUBLISHER]

Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 \mum process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency. [ABSTRACT FROM PUBLISHER]

In this paper, a component efficient multiple-input boost converter is proposed to extract power from multiple low-power energy harvesting sources. The time-multiplexed operation of the proposed converter enables sharing of the power stage between different input sources, leading to a reduced component count. Combined with a novel digital control method and a universal tracking algorithm, maximum power is automatically extracted for all the input sources. A dual-input prototype built with off-the-shelf components validates the overall strategy with commercially available energy transducers. A tracking efficiency of more than 97.5% is demonstrated. [ABSTRACT FROM PUBLISHER]

A new enhanced swing differential Colpitts VCO architecture enables oscillations to go beyond both the supply voltage and ground making it suitable for low voltage operation. Analysis for the oscillation frequency, differential- and common-mode oscillations, amplitude of oscillation, and start-up condition provides insight into oscillator operation and design considerations. Operating at 4.9 GHz, the VCO consumes from 1.9 mW to 3 mW for supply voltages of 400 mV and 500 mV, respectively. The 130 nm CMOS VCO's measured phase noise ranges from -132.6 to -136.2 dBc/Hz at a 3 MHz offset frequency. [ABSTRACT FROM AUTHOR]

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 \muW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of -112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz. [ABSTRACT FROM AUTHOR]