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Cyber-Physical Systems (CPSs) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, characterized for being smart, adaptive, predictive and react in real-time. Indeed, image- and video-processing pipelines are a prime source for environmental information for systems allowing them to take better decisions according to what they see. Therefore, in FitOptiVis, we are developing novel methods and tools to integrate complex image- and video-processing pipelines. FitOptiVis aims to deliver a reference architecture for describing and optimizing quality and resource management for imaging and video pipelines in CPSs both at design- and run-time. The architecture is concretized in low-power, high-performance, smart components, and in methods and tools for combined design-time and run-time multi-objective optimization and adaptation within system and environment constraints.

International audience; A major challenge for the European electronic industry is to enhance productivity by ensuring quality of development, integration and maintenance while reducing the associated costs. Model-Driven Engineering (MDE) principles and techniques have already shown promising capabilities, but they still need to scale up to support real-world scenarios implied by the full deployment and use of complex electronic components and systems. Moreover, maintaining efficient traceability, integration, and communication between two fundamental system life cycle phases (design time and runtime) is another challenge requiring the scalability of MDE. This paper presents an overview of the ECSEL1 project entitled “MegaModelling at runtime – Scalable model-based framework for continuous development and runtime validation of complex systems” (MegaM@Rt2), whose aim is to address the above mentioned challenges facing MDE. Driven by both large and small industrial enterprises, with the support of research partners and technology providers, MegaM@Rt2 aims to deliver a framework of tools and methods for: 1) system engineering/design and continuous development, 2) related runtime analysis and 3) global models and traceability management. Diverse industrial use cases (covering strategic domains such as aeronautics, railway, construction and telecommunications) will integrate and demonstrate the validity of the MegaM@Rt2 solution. This paper provides an overview of the MegaM@Rt2 project with respect to its approach, mission, objectives as well as to its implementation details. It further introduces the consortium as well as describes the work packages and few already produced deliverables.

Heterogeneous platforms are becoming widely diffused in the embedded system area, mainly because of the opportunities to increase application execution performance and, at the same time, to optimize other orthogonal metrics. In such a context, the introduction of mixed-criticality constraints, while considering heterogenous parallel architectures, creates new challenges to industrial and academic research. The main design issue is related to a Design Space Exploration (DSE) approach able to cope with mixed-criticality constraints that typically limits the number of feasible solutions. So, this work1 focuses on DSE for embedded systems based on heterogeneous parallel architectures and subjected to mixed-criticality constraints. In particular, it presents a criticality-driven evolutionary approach integrated into a reference Electronic System Level HW/SW Co-Design flow to support the designer of mixed-criticality embedded systems.

International audience; A major challenge for the European electronic industry is to enhance productivity while reducing costs and ensuring quality in development, integration and maintenance. Model-Driven Engineering (MDE) principles and techniques have already shown promising capabilities but still need to scale to support real-world scenarios implied by the full deployment and use of complex electronic components and systems. Moreover, maintaining efficient traceability, integration and communication between two fundamental system lifetime phases (design time and runtime) is another challenge facing scalability of MDE. This paper presents an overview of the ECSEL project entitled " MegaModelling at runtime – Scalable model-based framework for continuous development and runtime validation of complex systems " (MegaM@Rt2), whose aim is to address the above mentioned challenges facing MDE. Driven by both large and small industrial enterprises, with the support of research partners and technology providers, MegaM@Rt2 aims to deliver a framework of tools and methods for: 1) system engineering/design & continuous development, 2) related runtime analysis and 3) global model & traceability management, respectively. The diverse industrial use cases (covering domains such as aeronautics, railway, construction and telecommunications) will integrate and apply such a framework that shall demonstrate the validation of the MegaM@Rt2 solution.

Spatial and temporal isolation is a key issue in embedded systems running multiple tasks with different criticality levels (i.e. mixed-criticality embedded systems). This is particularly relevant for embedded systems based on multi core/processor (i.e. parallel) architectures. In such a context, this work focuses on Network on Chip (NoC) architectures and proposes a hardware mechanism designed to be introduced directly into network interfaces. Such a mechanism supports the isolation of multiple tasks with different criticality levels by controlling the exchange of messages while introducing very limited overhead on the monitored NoC. Then, the proposed mechanism is analyzed by means of two different simulations approaches for behavior validation, feasibility check, and scalability evaluation. The overall results show that the proposed mechanism is suitable to support mixed-criticality parallel embedded systems based on NoC architectures.

This work deals with the problem of developing embedded multi-core systems, under time-to-prototype and high performance constraints, by exploiting reconfigurable logic. In particular, the paper focuses on the early analysis activities, performed by means of native simulation technologies, and then on the full development of an embedded multi-core platform composed of four LEON3 soft-processors and able to support the execution of OpenMP based applications. Moreover, in order to evaluate software execution time at run-time, a distributed hardware profiling mechanism has been inserted into the final implementation to monitor the whole system. The final goal is the definition and the exploitation of a high-level design and validation methodology able to exploit both a well-known parallel execution paradigm and a run-time system monitoring service. Correctness and performance of such a platform have been evaluated by means of specific benchmarks.

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. This led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). This paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

VISION is an innovative infrastructure providing real-time sensing services, with particular emphasis on 3D video, with mobile and context-aware operation. Hence, it has addressed the numerous challenges raised by the limitations of current technology for wireless sensor networks. VISION exploits the 60 GHz ultra-wide band radios to enable broadband transmissions, miniaturized devices and reduced interference. Due to the inherent high resource consumption of broadband wireless necessary for real-time 3D video, VISION sensor network has been optimized at all layers. Novel techniques to manage the huge number of nodes required by ubiquitous sensing, and innovative tools to support the development process of intelligent services have been designed. Full cross-layer adaptability to external conditions assure the system will be able to manage the available resources to provide the best achievable quality of service guaranteeing graceful degradation for video, audio and sensing applications. The innovative sensor nodes based on above concepts are described in this paper, in relation to the selected scenario of Fire Rescue. The full hardware/software architecture is described and the challenges are discussed.

In this paper we present the most recent technological innovations introduced into the artistic installation we called RF Sounding, keep on maintaining our fundamental goals: creating an artistic installation that can be used for educational purposes as well. Indeed we have been inspired by the impossible human dream of flying that we reasoned on the acoustic dimension. We decided to make the inaudible, audible by a translation in the audio bandwidth of signals coming from cellular networks. We thus want to provide the user, entering the specifically defined area, with awareness of radio frequency signals characterizing the cellular networks band. With respect to the prototype presented in previous papers we finally exploit the information coming from a spectrum analyser, thus taking into account also the whole uplink, and position data acquired from a Microsoft Kinect in order to realize localization inside the equipped area, without the need for the users to wear an active device.

A Wireless Sensor Network (WSN) is a versatile and distributed sensing system that is able to support a wide variety of application domains. One of the most important issue in WSN design is to guarantee the reliability of the collected data which involves in turn security issues across wireless links. This paper deals with the cryptographic aspects in the broader field of security in WSNs. In particular, moving from some previous advances in our research activity, this manuscript proposes a novel cryptographic scheme that is compliant to security requirements that may arise from real-world WSN applications and reports some details about an implementation in TinyOS that we have carried for experimental validation. The proposed scheme, called TAKS2, exploits benefits from Hybrid Cryptography to handle resource constraints and allows to generate topology authenticated keys to provide increased robustness to the scheme itself.

Homeland security and monitoring of critical infrastructures, such as buildings, bridges, nuclear power plants, aircrafts, etc., represent challenging application domains for modern networking technologies. In this context Wireless Sensor Networks (WSNs) are gaining interest as a fundamental component of an advanced platform that embeds pervasive monitoring, networking and processing. Indeed, recent literature has addressed the perspectives of WSNs for monitoring structural and functional health of industrial plants, e.g. in (Akyildiz, et al., 2002; Bai et al., 2004; Barbaran et al., 2007; Cho et al., 2008; Flammini et al., 2008; Kim et al., 2007): nevertheless, we can observe that the dominating paradigm is to exploit WSNs features in terms of a “network of small sensors”, while almost unexplored is the more advanced paradigm of “networked smart sensors” and the underlying opportunity to actually support autonomous (anomaly) detection processes. A large body of specialized literature deals with this topic and several ad-hoc solutions can be found. On the contrary, we try to develop a different approach in this context: resorting to security mechanisms that are made available in traditional networks can provide a suitable and reliable framework, while smart adaptations are targeted to meet tight resource constraints and possible performance degradation.

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This paper presents a project that has been recently funded by means of the ERC Starting Grant (http://erc.europa.eu/). The main goal of the project is to develop a new generarion of wireless sensor networks infrastructure to support innovative services for ubiquitous sensing and video. The work is in a very preliminary phase so the paper presents a general overview and the main challenges.

A Wireless Sensor Network (WSN) is typically depicted as a distributed resource constrained platform for supporting novel pervasive applications. A possible approach is to develop applications over WSNs by resorting to mobile agent frameworks that are aimed to minimize resource costs and memory allocation. In this context, network topology is a major issue to be considered for resource optimization: for example, assuming that the underlying network topology for monitoring applications is a spanning tree, it is straightforward to see that converge-cast data flow patterns do not match with the any-cast requirement for agent mobility. Optimal spanning trees are expected to be short, balanced with a uniform density of agent instances. This paper focuses on the definition of a cost function, the related metrics and the supporting protocol to setup optimized spanning trees. The optimization procedure is able to account also for typical topology rearrangements induced by node faults in a WSN. Simulations have been performed and encouraging performance results are reported.

The demonstration proposal focuses on presenting the capabilities of a wireless biometric badge, which integrates a localization and tracking service along with an automatic personal identification mechanism, to control the access to restricted areas with a high level of security. The wireless biometric badge is the result of R&D activities conducted by several professors, researchers, and students in the Center of Excellence in Research DEWS at the University of L' Aquila in Italy, as well as its R&D Spin-Off WEST Aquila S.r.l.

Secure monitoring services supported by flexible, manageable, and cheap systems in areas where ordinary networks are unsuitable: this is one of to-day challenges in health monitoring engineering. Wireless Sensor Networks represent a promising technological solution but resource constraints and exposure to external attacks could limit their employment. The design and the implementation of an effective security to provide the monitoring service with the reasonable level of reliability is the scope of this paper. Following the platform-based design methodology, we have designed and implemented a “Secure Platform” to support Monitoring Applications which is compliant to requirements such as modularity, optimized usage of resource, solution scalability. To this aim, the Secure Platform exploits mobile agents and we have enhanced middleware solutions already available in literature. Security functions implemented in the Secure Platform have been a distributed intrusion detection system, based on a simplified approach to Hidden Markov Models, supported by an hybrid cryptographic scheme, based on network topology authentication. These security functions have been proposed by the same authors in [12] and [13]. Detailed design and the description of the software enhancements to the middleware platform are presented in this paper.

This work focuses on the analysis of fundamental issues which have to be considered in order to obtain voice from a wireless sensor network (WSN). The latter is assumed to be constituted by MicaZ wireless sensor nodes. Problems related to the transport of an audio signal through a wireless channel and sensor nodes are thus analyzed, and a project for an audio surveillance system is presented.

The demonstration focuses on presenting the capabilities of a wireless biometric badge integrating localization and tracking functionalities along with an automatic personal identification mechanism to control the access to restricted areas with a high level of security. The wireless biometric badge is the result of R&D activities conducted by several professors, researchers, and students from the Center of Excellence in Research DEWS at the University of L'Aquila in Italy, as well as its R&D Spin-Off WEST Aquila S.r.l.

This paper proposes a digital design methodology aiming at introducing certain degrees of reliability in case of hardware failures. Three main differences with respect to the traditional design methodologies for reliability are introduced: first, the peculiarities of the specification language are taken into account by exploiting the features of SystemC to introduce fault detection properties; second, different techniques are considered to determine the best cost/performance trade-off; third, the adoption of the desired reliability properties is carried out transparently to the designer. The three aspects together characterize the proposed approach, presented here through its application to a FIR circuit.

Mission-critical applications require that any failure that may lead to erroneous behavior and computation is detected and signaled as soon as possible in order not to jeopardize the entire system. Totally self-checking (TSC) systems are designed to be able to autonomously detect faults when they occur during normal circuit operation. Based on the adopted TSC design strategy and the goal pursued during circuit realization (e.g., area minimization), the circuit, although TSC, may not promptly detect the fault depending on the actual number of input configurations that serve as test vectors for each fault in the network. If such a number is limited, although TSC it may be improbable that the fault is detected once it occurs, causing detection and aliasing problems. The paper presents a design methodology, based on a circuit re-design approach and an evaluation function, for improving a TSC circuit promptness in detecting faults' occurrence, a property we will refer to as TSC quality.

In this paper, we showed how we exploited some of the system design capabilities of SystemC-Plus to model simple telecom cells. The significant benefits are the ease of modeling and the support of reuse. The combined use of specialization hierarchy and templates enables a wide applicability of the library. Another relevant value of the approach has been the possibility to cover two different application domains, like ATM and Internet, with similar Abstract Data Types.

This paper presents an approach for designing embedded systems able to tolerate hardware faults, defined as an evolution of our previous work proposing an hardware/software co-design framework for realizing reliable embedded systems. The framework is extended to support the designer in achieving embedded systems with fault tolerant properties minimizing overheads and limiting power consumption. A reference system architecture is proposed; the specific hardware/software implementation and reliability methodologies (to achieve the fault tolerance properties) are the result of an enhanced hw/sw partitioning process driven by the designer' constraints and by the reliability constraints, set at the beginning of the design process. By introducing also the reliability constraints during specification, the final system can benefit from the introduced redundancy also for performance gains, while limiting area, time, performance and power consumption overheads.

The reliability co-design project aims at integrating in a standard hw/sw co-design flow the elements for achieving a final system able to detect the occurrence of a fault during its operational life. The paper presents the focus of the project, the definition and identification of design methodologies for implementing the nominal, checking and checker functionalities either in hardware or in software. An outline of the system specification and system partitioning aspects is also provided.

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor. &nbsp

This paper presents the design of the CASPERmiddleware architecture that enables the implementation of real-time QoE-driven service management. More in detail, we thoroughly describe the new modules, methods and functionalities that need to be integrated into the network providers' infrastructure, according to CASPER. Based on this architecture, future virtualized networks can provide a closed-loop feedback environment that can act autonomously to maintain high levels of QoE with minimal human intervention. This is achieved via the proposed “QoE orchestrator”, which is responsible for implementing the QoE related logic.

Building on many discoveries and inventions, electronics started affecting people’s everyday lives in a significant fashion following the invention of the first solid state transistor in late 1940s. The miniaturization paved way for the mass electronics production and later the digital revolution, the outcomes of which are visible to all members of the public today. After about a two-decade-long swing around 2000s from hardware towards software regarding what affects lives more, a point has now been reached where electronics is more important to all and its use is more ubiquitous and crucial than ever before. In most if not all of end user or industrial applications, the capability and quality of electronics hardware are the key determining factors.The European electronics components and systems (ECS) industry has traditionally had a high base line for electronics innovation. However, the industry is now compelled, partly due to competition and partly due customer demand, to manufacture even more reliable electronics products than before. Guaranteeing the reliability of electronics hardware entails the entire ECS value chain to undergo a paradigm shift to holistically address reliability as a key issue. The European ECS industry previously adopted overseas outsourcing considerably, however it is now taking steps to reshape itself into a more coherent value chain with the aim of having not only the electronics designs but also the electronics manufacturing made in Europe.H2020-ECSEL programme successfully funds highly competitive projects in the area of electronics components and systems. We present here a prologue to a similarly funded project entitled Intelligent Reliability 4.0 ("iRel40"), by providing a background to the topic of ECS, project objectives, and the methodologies and implementations we plan to undertake during the 36-month period of this ongoing project.

In the frame of the CASPER project, we envision the performance evaluation of the new user-centric network and service management for future mobile networks. This paper extends our previous contribution on this subject by detailing a novel system level simulator built upon SimuLTE/OMNeT + + to assess quality of experience (QoE)-aware management policies in real LTE networking conditions with Voice over IP and video streaming traffic patterns. The results demonstrate that an accurate choice of the design parameters both at the application layer and at the network layer is paramount to achieve acceptable QoE levels over the time.

The development, deployment and real-world validation of software based on IEEE 802.15.4 standard (and its derivations, e.g. 15.4e), require the exploitation of a Testbed as the network grows in complexity and heterogeneity. Many companies provide different implementations of software frameworks that aim to handle the process of reserving and providing resources to developers. Testbed-Federations aggregate different Testbed projects under unified discovery and reservation tools and are supported by research founds. Those Testbed-Federations are general purpose in terms of network interface handling. Trying to compete with those giants is unfair so LabSMILING is focused on a smaller domain providing an optimized Testbed designed for IEEE 802.15.4-based Wireless Sensor Networks (WSN). Thanks to the reduced field of application, LabSMILING can focus on specific topics and can address them providing a higher-level user experience for developers supported by a customized core system.

Heterogeneous devices are becoming widely diffused in the embedded system domain, mainly because of the opportunities to increase application execution performance and, at the same time, to substantially reduce energy consumption. In such a context, this work faces the role of HW/SW co-simulators/analysis tools for embedded systems based on heterogeneous parallel architectures. In particular, it presents a SystemC-based tool for functional/timing HW/SW co-simulation and analysis within a reference ESL HW/SW co-design flow. The description of the main features of the tool, the main design and integration issues and an illustrative case study represent the core of the paper.

This work faces the role of Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subject to mixed-criticality system requirements, while considering the exploitation of hypervisor-based SW partitions to better manage isolation. In particular, it presents an evolutionary partitioning and mapping approach integrated into a reference Electronic System Level HW/SW Co-Design framework to propose and early validate design solutions by means of HW/SW Co-Simulations.

In recent years, the use of multiprocessor systems has become increasingly common. Even in the embedded domain, the development of platforms based on multiprocessor systems or the porting of legacy single-core applications are frequent needs. However, such designs are often complicated, as embedded systems are characterized by numerous non-functional requirements and a tight hardware/software integration. This work proposes a methodology for the development and validation of an embedded multiprocessor system. Specifically, the proposed method assumes the use of a portable, open source API to support the parallelization and the possibility of prototyping the system on a field-programmable gate array. On this basis, the proposed flow allows an early exploration of the hardware configuration space, a preliminary estimate of performance, and the rapid development of a system able to satisfy the design specifications. An accurate assessment of the actual performance of the system is then enforced by the use of an hardware-based profiling subsystem. The proposed design flow is described, and a version specifically designed for LEON3 processor is presented and validated. The application of the proposed methodology in a real case of industrial study is then presented and analyzed.