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The infiltrative nature of lesions is a significant feature of malignant breast lesion on ultrasound image. Characterizing the infiltrative nature of lesions with computationally inexpensive and highly efficacious features is crucial for the realization of a computer-aided diagnosis system. In this study, the infiltrative nature is regarded as an energy that produces irregularly and considerably local variances in a 1-D signal. The local variances can be characterized by a few high octave energies (i.e., the channel energies close to low-frequency bands) in a 1-D discrete periodic wavelet transform. For computational cost reduction, high octave decomposition is performed by a reversible round-off 1-D nonrecursive discrete periodic wavelet transform. A test dataset of breast sonograms with the lesion contour delineated by an experienced physician and two inexperienced persons is built for feature efficacy evaluation. High individual performance results imply that the proposed feature is well correlated with the diagnosis of the experienced physician. Experimental results also reveal that with a great performance improvement, the proposed feature is suitable for the combination with some morphometric parameters. Index Terms--Breast lesion classification, octave energy, reversible round-off 1-D nonrecursive discrete periodic wavelet transform (RRO-NRDPWT), roughness description.

In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 x 4 inverse integer transform, the 4 x 4 inverse Hadamard transform and the 2 x 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format. Index Terms--H264/AVC, residue decoder, VLSI.

In this paper, efficient recursive structures for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) and its inverse DCT (IDCT) are proposed. The M-D DCT and IDCT are first converted into condensed one-dimensional (1-D) DCT and discrete sine transform (DST) with a regular preprocessing procedure. The recursive filters for condensed 1-D DCT/DST are then derived by using Chebyshev polynomials to compute M-D DCT/IDCT without data transposition. The proposed structures require fewer recursive loops than traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than traditional row-column structures. The proposed recursive M-D DCT/IDCT structures are suitable for very large-scale integration implementation due to regular and modular features. Index Terms--Discrete cosine transform (DCT), fast algorithm, inverse DCT (IDCT), multidimensional signal processing, recursive structure.

This paper presents a discrete-cosine transform (DCT)-based adaptive thresholding algorithm to achieve an effective binarization of video image for binary motion estimation (BME). The BME through the full search mechanism requires extremely low hardware complexity. Experimental results show that the proposed adaptive BME attains performance close to the 8-bit resolution ME for low motion sequences with full search strategy. Compared to the well-known single-layer BME, the proposed adaptive algorithm shows better peak signal-to-noise ratio performance and more robustness to complex images. Moreover, the proposed algorithm has a lower computational complexity that is suitable for VLSI implementation with a smaller hardware overhead. Index Terms--discrete cosine transform (DCT)-based adaptive thresholding (DAT), binary motion estimation (BME), fast motion estimation, fast motion search, DCT.

In this paper, new recursive structures for computing radix-r two-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse DCT (IDCT) are proposed. The 2-D DCT/IDCT are first decomposed into cosine-cosine and sine--sine transforms. Based on indexes of transform bases, the regular pre-addition preprocess is established and the recursive structures for 2-D DCT/IDCT, which can be realized in a second-order infinite-impulse response (IIR) filter, are derived without involving any transposition procedure. For computation of 2-D DCT/IDCT, the recursive loops of the proposed structures are less than that of one-dimensional DCT/IDCT recursive structures, which require data transposition to achieve the so-railed row--column approach. With advantages of fewer recursive loops and no transposition, the proposed recursive structures achieve more accurate results and less power consumption than the existed methods. The regular and modular properties are suitable for very large-scale integration (VLSI) implementation. By using similar procedures, the recursive structures for 2-D DST and 2-D IDST are also proposed. Index Terms--Discrete cosine transform (DCT), fast algorithm, inverse DCT (IDCT), multidimensional signal processing, recursive structure.

A CMOS rail-to-rail comparator operating at low-voltage supply by using a conventional fabrication process is proposed. Based on the comparator, an analog rank-order extractor with [kappa] winner-take-all capability is presented. An experimental chip was fabricated using 0.5 [micro]m CMOS technology. Measured results at 1-V supply voltage show a comparator response time of 4 [micro]s for 10-mV precision and that the extractor within 4[micro]s successfully identifies a 100-mV differential voltage among inputs to find a rank order of the input set. Index Terms--Comparator, low-voltage circuit, rank-order extractor.

In this paper, an adaptive postprocessor figured with discrete cosine transform (DCT)-based block classification to effectively remove the so-called blocky effect from compressed video sequences is proposed. The proposed DCT-based detection algorithms for both intraframes and interframes require much lower computation complexity than the spatial-domain approaches. In order to preserve the edge information, the adaptive postprocessor is also designed with a DCT-based edge detection mechanism such that a one-dimensional median filter can be adaptively adjusted to match with the edge orientation. Simulation results show that the proposed DCT-based detection algorithms accurately classifies smooth, edge, or nonsmooth blocks to help the adaptive postprocessor to effectively remove the blocky effect and sharply preserve the edge information. Index Terms--Adaptive median filter, transform coding, video coding, video signal processing.

H.264, MPEG-4 Part 10, is the latest digital video coding standard that achieves very high data compression by using several new coding features. One of the new features is variable block sizes for interframe coding to increase compression efficiency. However, to achieve this, the H.264 encoder employs a complex mode decision technique based on rate-distortion optimization (RDO) that requires high computational complexity, which significantly increases the encoder complexity. In this paper, we propose a classified region algorithm(CRA) that analyzes the spatial and temporal homogeneity of the block by using cross differences to reduce the number of modes that are required for RDO calculation in inter mode decision. The proposed low computational complexity algorithm significantly reduces the number of inter modes without affecting the video quality. The experimental results show that the proposed method is able to reduce complexity by up to 67% on average with negligible degradation in both objective and subjective quality.

The stability for cellular neural networks (CNNs) with time-varying delay is introduced by linear-matrix inequality. A sufficient condition related to the global asymptotic stability for delay CNNs is proposed. It is shown that the condition relies on the dependence of the delay. This condition is less restrictive than that given in the literature. Index Terms--Cellular neural networks (CNNs), linear-matrix inequality (LMI), stability.

In this paper, a stereoview to multiview conversion system, which includes stereo matching and depth image-based rendering (DIBR) hardware designs, is proposed. To achieve an efficient architecture, the proposed stereo matching algorithm simply generates the raw matching costs and aggregates cost based on 1D iterative aggregation schemes. For the DIBR architecture, an inpainting-based method is used to find the most similar patch from the background, according to depth information. The simulation results show that the designed architecture achieves an averaged peak signal-to-noise ratio of 30.2 dB and structure similarity of 0.94 for the tested images. The hardware design for the proposed 2D to 3D conversion system operates at a maximum clock frequency of 160.2 MHz for outputting 1080p ($1920 \times 1080$) video at 60 frames per second. [ABSTRACT FROM AUTHOR]

This paper presents a three-electrode potentiostat transducer circuit for electrochemical sensing system designed for biomolecular detection. Melatonin has been found to be used as a significant index of potential breast cancer risk. The proposed chip automatically measures the redox current which depends on the concentration of melatonin in the analyte solution. Moreover, a current-to-time converter is designed to convert the sensed current into the proportional digitized time signal for back-end signal processing. Cyclic voltammetry and molecularly imprinted polymers were used in the experiments. The sensing electrodes were coated with a thin film imprinted with the target molecule. Fabricated in the TSMC CMOS 0.18 μm 1P6M technology, the proposed chip has a core chip size of 0.083 mm2 and a power consumption of 1.143 mW with a 1.8 V supply voltage. This chip can measure the sensed current from ±15 to ±1500 µA with a linearity of R2 = 0.999. In the cyclic voltammetry measurement, this chip has an error of less than 0.7%. The urine measurement results of the proposed chip were compared with that of enzyme-linked immune sorbent assay. Verified by melatonin concentration measurement, the proposed chip with high sensitivity demonstrates the feasibility of melatonin concentration detection, which contributes to the examination of breast cancer. [ABSTRACT FROM AUTHOR]

Electrochemical impedance spectroscopy (EIS) is a widely used technique in biomedical and chemical analysis. A novel 10-bit impedance-to-digital converter (IDC), which can measure and directly convert the magnitude and phase of impedance to digital codes, is proposed for the EIS measurement system. The proposed IDC is composed of a magnitude-to-digital converter (MDC) and a phase-to-digital converter (PDC). The proposed IDC was designed and fabricated using a 0.35 \mu\textm 2P4M mixed-signal polycide process, and the core area is only 0.07 mm2. Moreover, it can work over a very wide frequency range (0.1 mHz–100 kHz), and has excellent accuracy. According to the measured results, the DNL of the MDC is within −0.3/+0.3 LSB, and the INL is around −3/+1 LSB. Moreover, an EIS measurement system, which is composed of the proposed IDC chip and some other commercial chips, is built to measure ZoBell’s and melatonin solutions for validating the function of the proposed IDC. [ABSTRACT FROM PUBLISHER]

The high‐efficiency video coding (HEVC) standard for three‐dimensional (3D) video, which is called 3D‐HEVC, improves the compression efficiency for high resolution 3D video sequences. In this study, three coding time reduction algorithms, namely fast coding unit partition, fast prediction unit (PU) partition and search range reduction, are proposed for inter‐prediction of 3D‐HEVC by referring to the depth edge information. The pixels in one object should have the same motion characteristics. By detecting depth edge, we can easily classify the regional pixels if they are in the same object. Thus, in the encoding stage, the sizes of coding and PUs can be determined by the proposed fast coding unit partition and fast PU partition methods, respectively. Furthermore, the range of motion search can be effectively reduced by the proposed search range reduction method. Experimental results show that the proposed depth edge‐based motion search algorithms can reduce the coding time of inter‐prediction by up to 62% on average with negligible quality degradation. [ABSTRACT FROM AUTHOR]

A filter-based wide-range programmable sinusoidal wave synthesizer for electrochemical impedance spectroscopy measurement is proposed. The adopted filter is implemented with switched-capacitor circuits, so its corner frequency is accurate and adjustable by changing its switching frequency. The proposed sine wave synthesizer is implemented by using a 0.35 \,\mum 2P4M 3.3 V mixed-signal polycide process. According to the measured results, the output frequency of the proposed synthesizer is 40 mHz–40 kHz . The measured total harmonic distortion is 0.073% at 10 Hz and 0.075% at 10 kHz, both of which are better than that of a typical function generator. [ABSTRACT FROM PUBLISHER]