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In this paper, a new realization of electronically controllable positive and negative floating capacitor multiplier (±C) is presented. The peculiarity of the presented topology is that, for the first time, it implements a floating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII±) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage VC which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µm and ±0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ±10 to ±25.4 with a maximum error of 0.56%. As an example, the application of the achieved floating capacitor as a standard high pass filter is also included.

In this paper, an implementation of a simulated grounded inductor (SGI) based on a recently developed active building block called second-generation voltage conveyor (VCII) is proposed. The proposed SGI employs two VCIIs, two resistors, and one grounded capacitor, which is preferred when integration is involved. More importantly, unlike most of the other previously reported SGIs, this one is free from any restrictive matching conditions. A complete analysis of nonidealities along with sensitivity treatment by considering parasitic impedances and nonideal gains of the VCII are performed. A simple VCII circuit is designed to be used in the implementation of the proposed SGI. To support the presented theory, Pspice simulation results using 0.18-µm CMOS technology parameters and supply voltage of ±0.9 V are provided. On the basis of the achieved results, the proposed SGI operates in a good agreement with an ideal inductor. The power consumption is only 0.65 mW, and the parasitic series impedance is approximately 191.9 ?. The applicability of the proposed SGI is tested by using it in a standard second-order high-pass RLC filter. © 2020 John Wiley & Sons, Ltd.

In this paper we propose a new versatile full wave rectifier circuit using voltage conveyor (VCs) as active blocks. The proposed circuit uses two VCs, a single grounded resistor and two diodes. Compared to other previously reported rectifier circuits, it shows a simple and compact structure, employing the minimum possible number of elements. Moreover, the rectified output is available in forms of both voltage and current signals, at low impedance voltage output Z port and high impedance X port of VC, respectively. Therefore, for practical use, the proposed rectifier is cascadable without the need for extra voltage and current buffers. In addition, also the input signal can be applied in both forms of a current and of a voltage. To validate the presented theory, SPICE simulations, using 0.35 µm CMOS technology parameters and supply voltage of ±1.65 V, are reported, together with a set of measurements conducted over an equivalent discrete-level circuit, where AD844s were used to mimic VCs behavior.

In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage operation capabilities is presented. Simplicity is other important feature so that the whole circuit is composed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-threshold region. The required current-controlled gain stage has been implemented using an appropriate translinear loop which is fed by the output of a current subtraction stage, realized through the employment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is evaluated through simulation results, using the Cadence suite and MOS transistors models provided by the Austria Mikro Systeme 0.35 μ m CMOS process. The differential gain was 20 – 40 dB , the Common-Mode Rejection Ratio (CMRR) was 44.4 – 48.9 dB , achieved at power dissipation 72.75 – 386.1 nW . The bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2 % for an input signal with amplitude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier has been employed for removing the noise component in electrocardiogram signals.

A new low-voltage low-power class-AB second generation voltage conveyor (VCII) is presented. The proposed circuit is based on an improved class-AB flipped voltage follower (FVF) designed by adding a simple negative feedback loop to the conventional class-AB circuit. This modification ensures high current drive capability of at least 2 mA for both falling and rising edges of input signal along with very low 2- $\text{m}{\Omega }$ output impedance and high accuracy. Benefiting from the new class-AB FVF, the proposed VCII features a very simple implementation, extremely low impedance at $Y$ and $Z$ terminals (2 $\text{m}{\Omega }$ ), high impedance at $X$ terminal (370 $\text{k}{\Omega }$ ) and high accuracy in current and voltage conveying (99% and 98%, respectively). Moreover, it exhibits current drive capability 117.6 times larger than its bias current ( $17~\mu \text{A}$ ). The circuit occupies $381.5\,\,\mu \text{m}\,\,\times 197\,\,\mu \text{m}$ area. The application of the proposed VCII as a voltage integrator is also presented. Simulation results using PSpice and 0.35- $\mu \text{m}$ CMOS technology with ±1.65-V supply voltage are provided to demonstrate the presented theory. A comparison with the literature is also provided.

A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 µm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters. © The Institution of Engineering and Technology 2020

Although the idea of second generation voltage conveyor (VCII) dates back to two decades ago, only in a recent publication by authors, its applications and capabilities were studied. Considering that VCII-based circuits are also realizable by Operational Amplifiers (Op-Amps), in this paper a comparison between circuits implementable using either Op-Amp or VCII is drawn. The transfer function and main characteristics of each implementation are given. To validate the presented theory Spice simulations performed in 0.18 µm CMOS technology with a supply voltage of ±0.9 V are provided. The achieved results show that the circuits based on Op-Amp require a very high gain for this active block, to be traded off with bandwidth. As a consequence, Op-Amp can be successfully replaced by VCII for high frequency applications. In addition, the output of Op-Amp based circuits is of inverting (or non-inverting) type while both inverting and non-inverting outputs are achievable in the VCII based circuits. Other benefits are achieved: more importantly, using VCII to implement non-inverting voltage summing circuit is an effective solution to remove the undesired cross-talk effect that occurs in Op-Amp based one. PSpice simulations complete the comparison.

In this chapter, Current-Mode Instrumentation Amplifiers (CMIAs) with the capability of having an electronically controllable gain are discussed. These CMIAs do not require variable passive resistors to change gain but the latter is adjusted by means of a control voltage or current. This kind of instrumentation amplifiers is more suitable for IC realization. We divide electronically controllable CMIAs into two categories. In the first category, gain is varied by means of either bias current or bias voltage of the used active building blocks. Here, electronic controllability is achieved at the expense of higher power consumption. In the second category, gain is varied by means of an electronically variable active resistor. Therefore, they have much simpler design and show less power consumption. © 2019, Springer Nature Switzerland AG.

In vast majority of operational amplifiers, output transistor current is not independently accessible. Op-Amp power supply current sensing is a simple technique for detecting output transistor current from the Op-Amp power supply leads. This technique was first introduced in 1979 to implement voltage controlled current sources and current controlled current sources [1]. It has been implemented by connecting current mirrors to Op-Amp supply leads and makes possible to gain access to output transistor current separately. © 2019, Springer Nature Switzerland AG.

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 &mu, m CMOS technology parameters at a supply voltage of &plusmn, 0.9 V are provided to support the presented theory.

In this chapter, current-mode instrumentation amplifiers (CMIA) suitable for biomedical and low-voltage low-power applications are reviewed. The design requirements and the techniques used to meet them are discussed. One of the major problems of biomedical interfaces is the necessity to attach at least three electrodes to patient body which causes discomfort and increases the power consumption. The CCII-based bootstrapping technique used to design a two-electrode low-voltage low-power interface circuit is discussed. Due to the advances in CMOS technology and the reduced supply voltages, similar to conventional 3 Op-Amp based IAs, the voltage input-voltage output CMIAs also require high common-mode input and output ranges. Different low-voltage methods used to improve common-mode input and output ranges are also discussed. © 2019, Springer Nature Switzerland AG.

In this paper, a novel approach to implement a stray insensitive CMOS interface for differential capacitive sensors is presented. The proposed circuit employs, for the first time, second-generation voltage conveyors (VCIIs) and produces an output voltage proportional to differential capacitor changes. Using VCIIs as active devices inherently allows the circuit to process the signal in the current domain, and hence, to benefit from its intrinsic advantages, such as high speed and simple implementation, while still being able to natively interface with voltage mode signal processing stages at necessity. The insensitiveness to the effects of parasitic capacitances is achieved through a simple feedback loop. In addition, the proposed circuit shows a very simple and switch-free structure (which can be used for both linear and hyperbolic sensors), improving its accuracy. The readout circuit was designed in a standard 0.35 &mu, m CMOS technology under a supply voltage of &plusmn, 1.65 V. Before the integrated circuit fabrication, to produce tangible proof of the effectiveness of the proposed architecture, a discrete version of the circuit was also prototyped using AD844 and LF411 to implement a discrete VCII. The achieved measurement results are in good agreement with theory and simulations, showing a constant sensitivity up to 412 mV/pF, a maximum linearity error of 1.9%FS, and acknowledging a good behavior with low baseline capacitive sensors (10 pF in the proposed measurements). A final table is also given to summarize the key specs of the proposed work comparing them to the available literature.

This brief presents a comprehensive study on a particular kind of conveyor called second-generation voltage conveyor (VCII). This building block is based on voltage conveying concept and is the dual of second generation current conveyor (CCII). It is shown that VCII is a very useful block in those configurations where CCII is limited, in terms of number of active blocks. The results of this brief are helpful in choosing the best building block between CCII and VCII for each specific application. Finally, for the first time, the CMOS implementation of VCII is also presented. Simulation results with PSPICE using 0.35- ${\mu }\text{m}$ CMOS technology and supply voltage of ±1.65 V are given to approve the theory.

Minaei, Shahram (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2018; Florence; Italy; 27 May 2018 through 30 May 2018. Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.

In this paper, a new low-power versatile current-mode rectifier is proposed. As a salient feature, the proposed rectifier provides two positive half-wave, two inverting negative half-wave or two full-wave outputs from the same configuration. The proposed circuit employs only a dual-output second-generation current conveyor (DO-CCII) and a core rectifying circuit consisting of twelve MOS transistors. The input and output signals are current. Favorably, by adding two additional transistors, the proposed rectifier can also rectify voltage signals with electronic tuning capability. The simple and MOS only structure of the proposed circuit is highly attractive from integration point of view. In spite of providing multiple outputs at the same time, the proposed rectifier enjoys low power consumption. PSPICE simulations using 0.18 mu m CMOS parameters and supply voltage of +/- 0.9 V demonstrate a precise operation and good temperature stability. (C) 2017 Elsevier GmbH. All rights reserved.

Minaei, Shahram (Dogus Author) In this paper a new topology for implementing Current-Mode Instrumentation Amplifiers (CMIA) is presented. The proposed CMIA is based on two single input-multiple output (SI-MO) current operational amplifiers (COAs) as basic building blocks and 2 resistors. To electronically control the differential mode gain, a transistor operating in triode region is used which acts as a variable resistor. The significant feature of the proposed CMIA is that the active building blocks operate in closed loop configuration. Therefore it exhibits numerous remarkable features such as improved frequency performance, low THD and very low input impedance. In addition, it has fully differential output which reduces the output noise and increases its application. The proposed CMIA is analyzed and simulated with SPICE program using parameters of 0.18 mu m CMOS technology and supply voltage of +/- 0.9 V.

Minaei, Shahram (Dogus Author) In this paper, a new electronically tunable current-mode (CM) first-order universal filter as a new application for inverting second-generation current conveyors (ICCIIs) is proposed. The proposed circuit is based on two ICCII and a capacitor and does not need any resistors and critical passive component matching conditions. It has one input and multiple outputs and simultaneously realizes both inverting and non-inverting first-order low-pass, high-pass and all-pass responses from the same configuration. Employing ICCII as active building block makes possible using a single transistor in linear region as a variable resistor to control filter properties electronically. Nevertheless, the proposed CM first-order universal filter possesses a floating capacitor which can be easily realized in nowadays integrated circuit technologies. It is designed and simulated with SPICE program using 0.13 mu m IBM CMOS parameters and supply voltage of +/- 0.75 V. Non-ideal analysis and Monte Carlo simulation results are also given, which prove good enough response even in the presence of non-idealities and process parameter variations.

Minaei, Shahram (Dogus Author) -- Conference full title: 2017 European Conference on Circuit Theory and Design (ECCTD); Catania; Italy; 4-6 September 2017. In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its input and output signals are current and it enjoys low input and high output impedances, respectively. Due to the inefficiency of the existing ECCIIs, a new ECCII circuit is also designed to be used in the proposed CMIA structure. PSPICE simulation results using 0.18μm TSMC CMOS technology and supply voltage of ±0.9V, shows CMRR of 42dB and fixed -3dB bandwidth of 68MHz for differential-mode gain ranging from 0dB to 27dB.

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18[Formula: see text][Formula: see text]m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68[Formula: see text]k[Formula: see text], respectively. Time domain analysis shows that for an input signal of 20[Formula: see text][Formula: see text]A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only [Formula: see text].

Minaei, Shahram (Dogus Author) -- Conference full title: 2016 39th International Conference on Telecommunications and Signal Processing, TSP : June 27-29, 2016, Vienna, Austria. A New CMOS resistor based current mirror with extremely low voltage requirement at input (in the range of a few mV) and output voltage requirement of about one Vds is presented. The proposed structure combines the advantages of wide input swing, wide output swing, large output impedance, low input impedance and high linearity altogether, which make it attractive for high performance low-voltage and low power applications. Pspice simulations show a very low THD of -42.2dB from a single 0.9V supply in 0.18μm, input impedance of 239Ω, output impedance of 1.2MΩ and power dissipation of only 180μW. Interestingly, the input and output voltage requirements are only 10mV and 0.1V respectively.

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.

In this paper, a novel first-order current-mode (CM) electronically tunable all-pass filter including one grounded capacitor and two dual-output current followers (DO-CFs) is presented. The used DO-CFs are implemented using only 10 MOS transistors granting the proposed CM all-pass filter extremely simple structure. The proposed filter is suitable for integrated circuit (IC) fabrication because it employs only a grounded capacitor and is free from passive component matching conditions. Interestingly the introduced configuration uses minimum number of components compared to other works. It also offers other interesting advantages such as, alleviating all disadvantages associated with the use of resistors, easy cascadability and satisfies all technology requirements such as small sizing, simple realization, low voltage and low power operation. Additionally, the circuit parameters can be easily set by adjusting control voltages. Most favorably, the proposed CM all-pass filter can be simply used as a voltage-mode (VM) all-pass filter with outstanding properties of adjustable gain and tunability. To further show the versatility of the proposed structure a sinusoidal oscillator is also derived from presented CM all-pass filter. Nonideal gain and parasitic impedance effects on developed CM filter are discussed. Finally, simulation results with SPICE program are included to confirm the theory. © 2013 World Scientific Publishing Company.

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 mu m CMOS technology parameters and a supply voltage of +/- 0.9 V. The small signal impedance values were 973 Omega, 120 k Omega and 217 Omega at Y, X and Z ports, respectively. The maximum current at the X port was +/- 10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (I-B) of 29 mu A and output current at the X port (I-X) of 10 mA, the current drive capability (I-X/I-B) of about 345 was achieved at the X port. The voltage swing at the Z port was (-0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 mu W. innovation project iRel4.0 ECSEL [876659] This research has been partially founded by the European co-funded innovation project iRel4.0 ECSEL under grant agreement No 876659.