1. A discussion on how to define the tolerance for line-edge or linewidth roughness and its measurement methodology
- Author
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Yamaguchi, Atsuko, Steffen, Robert, Kawada, Hiroki, Iizumi, Takashi, and Sugimoto, Aritoshi
- Subjects
Mensuration -- Methods ,Metal oxide semiconductor field effect transistors -- Properties ,Business ,Computers ,Electronics ,Electronics and electrical industries - Abstract
A metrological definition and a target value for linewidth roughness (LWR) in a gate pattern of MOSFETS are proposed. The effects of sampling interval gate-LWR measurements by critical-dimension scanning electron microscopy on measurement accuracy were examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-[micro]m-long line. Random image noise and intrinsic LWR variations are found to have larger effects on the measured LWR value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also devised. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is determined from the LWR spectrum and the I-V curves of a transistor without LWR (i.e., ideal I-V curves). Index Terms--Line-edge roughness (LER), linewidth roughness (LWR), MOSFET.
- Published
- 2007