1. Perspective of tunnel-FET for future low-power technology nodes
- Author
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M.M. Heyns, Nadine Collaert, K. De Meyer, Quentin Smets, Rita Rooyackers, Anne Vandooren, Anda Mocuta, Guido Groeseneken, A. V-Y. Thean, M. L. Van de Put, K-H. Kao, Bart Sorée, Anne S. Verhulst, and Devin Verreck
- Subjects
Computer. Automation ,Materials science ,business.industry ,Perspective (graphical) ,Optoelectronics ,Heterojunction ,Dielectric ,business ,Quantum tunnelling ,Domain (software engineering) ,Power (physics) - Abstract
Theoretically, confined heterostructure p(-n)-i-n (n(-p)-i-p) TFETs are promising candidates for future low-power applications, with n-TFET outperforming p-TFET. An optimal body thickness of about 10nm is predicted for Ga 0.5 As 0.5 Sb-In 0.53 Ga 0.47 As n-TFET with I 60 =20µA/µm. For p-TFETs, stronger confinement may be required to avoid tunneling to the heavy-hole band. An unexploited domain is the insertion of thin heterostructure slabs offering a locally reduced dielectric constant, enhancing both SS and I on .
- Published
- 2014