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Made available in DSpace on 2022-04-28T19:41:36Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-12-01 An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University Imec ClaRoo E.E. Dept KU Leuven UNESP Sao Paulo State University

Made available in DSpace on 2022-04-28T19:40:54Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-10-01 The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz. Imec, Kapeldreef 75 Universidade Tecnológica Federal do Paraná UNESP Sao Paulo State University LSI/PSI/USP University of Sao Paulo EE Depart. KU Leuven, Kasteelpark Arenberg 10 UNESP Sao Paulo State University

Made available in DSpace on 2022-04-28T19:42:42Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-09-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Current mirrors (CMs) are essential building blocks for biasing integrated circuits. The gate-all-around silicon nanosheet MOSFETs (GAA-NS) are excellent candidates for the sub 7 nm technology node. In this work, CMs designed with GAA-NS are studied for the first time. This study is performed from room temperature to 200 ◦C using Verilog-A with Look Up Table based on experimental data of n- and p-type GAA-NS for circuit simulation. The current source (reference current) that supplies the CM is designed with an inverter with feedback for simplicity. Due to the zero temperature coefficient (ZTC) region, multiple designs are made to evaluate each type of biasing (before, after and in the ZTC region). Symmetric and asymmetric VTH for n- and p-type GAA-NS are also analyzed. The asymmetric approach presents a compliance voltage of 0.7 V and 0.8 V, for an n- and p-mirror, respectively, while the symmetric one yields a compliance voltage of 0.75 V for both mirror types, and errors lower than 6%, for the design biasing the transistors before the ZTC region. LSI/PSI/USP University of Sao Paulo Imec UNESP Sao Paulo State University UNESP Sao Paulo State University

Made available in DSpace on 2022-04-28T19:44:05Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-08-23 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) — In this work we further investigate the operation of theBESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is applied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University UNESP Sao Paulo State University CAPES: 2017/26489-7 CNPq: 2017/26489-7 FAPESP: 2017/26489-7

Made available in DSpace on 2022-04-28T17:20:13Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-07-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) The analysis of vertically stacked nanosheet (NS) n-type transistors with two different metal gate-stacks (with a total thickness of 7.5 and 4.7 nm) is presented in this work from room temperature to 200 degrees C. The focus in this work is on the classical analog figures of merit (FoM). In all NS devices, superior performance is observed that is confirmed by the subthreshold swing variation with temperature, which is very close to the theoretical thermal limit. The Al-based (n*) gate-stack NS n-channel NS field effect transistors (NSFETs) in general present higher transconductance, transistor efficiency, early voltage, and intrinsic voltage gain (A(V)) thanks to the better electrostatic coupling between the gates and the silicon NSs. An A(V) of about 47 dB (gate-stack (n*), L = 200 nm, 200 degrees C) is obtained. The low-frequency noise analysis demonstrates the presence of flicker noise dominated by carrier number fluctuations as the main type of noise and presents a low current noise power spectral density Sid of 10(-19) A(2)/Hz at a drain current of 1 mu A and a drain voltage of 50 mV for a frequency of 10 Hz. Univ Sao Paulo, BR-05508010 Sao Paulo, Brazil IMEC, B-3001 Leuven, Belgium Univ Sao Paulo, PSI Elect Syst Engn Dept, BR-05508010 Sao Paulo, Brazil Sao Paulo State Univ, Dept Elect & Telecommun Engn, BR-13876750 Sao Joao Da Boa Vista, Brazil Sao Paulo State Univ, Dept Elect & Telecommun Engn, BR-13876750 Sao Joao Da Boa Vista, Brazil

In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths (W fin) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region (g m/I D = 8 V−1). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.

In this paper, we present a comprehensive study of the Fringing Field Biosensor Tunnel-FET (Bio-TFET) device based on 2D-device simulation. The presence of a biomaterial with a distinct dielectric constant (k, where ε = k*ε 0) on the underlap region (LUD) between gate and drain affects the ambipolar drain current (ID). The Bio-TFET can be observed in the ambipolar region (i.e., for negative gate voltage in an n type Bio-nTFET device) due to the variation of the k, biomaterial thicknesses (tBio), the LUD, and/or the presence of charges (QBio) into the biomaterial/silicon interface. The results show that the maximum sensitivity is observed when LUD = 30 nm (3 orders of magnitude higher compared with LUD of 25 nm lower or higher than 30 nm). When tBio increases from 10 nm to 30 nm (for k = 10), the sensitivity increases up to 1 orders of magnitude. The presence of QBio into the biomaterial also increases the sensitivity of 60 times for a fixed value of tBio = 30 nm and k = 10 and QBio changing from 1 × 1010 cm−2 to 1 × 1012 cm−2. The results show that the sensitivity of the fringing field Bio-nTFET is strongly dependent on the tunneling length modulation.

Made available in DSpace on 2022-04-28T19:42:10Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-01-01 An evaluation of a dielectrically modulated (DM) and a fringing field (FF) biosensor based on a tunneling field-effect transistor (Bio-TFET) by 2D numerical simulation is presented. The bio detection is based on the presence of a biomaterial with a distinct dielectric constant (k) on the sensitivity area. The performance of the devices is compared in terms of drain current in the ambipolar region (i.e., for negative gate voltage in an n-type Bio-nTFET device) due to the variation of the k, drain underlap length (LUD), and the presence of charges (QBio) into the biomaterial/silicon interface. The results show that the DM biosensor with LUD = 25 nm exhibits a higher sensitivity in all k simulated compared with FF biosensor, resulting in more than 2 orders of magnitude for k = 10. In the presence of charges, the DM shows a higher sensitivity in all of the range studied. Higher sensitivity values over a wider range of LUD and QBio are desirable and DM Bio-TFET achieves a better result compared with the FF Bio-TFET. Results show a new outlook for each type of biosensor. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University UNESP Sao Paulo State University

Made available in DSpace on 2020-12-10T17:40:00Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-09-01 Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) In this paper operational transconductance amplifiers (OTA) were designed with nanowire (NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) and compared with NW Si MOSFET devices. Lookup tables with experimental data were used to model the transistors and simulate the OTAs. At the same dimensions and transistor efficiency region, the TFET OTAs have larger gain than the MOSFET circuit. The Ge-source TFET OTA presents the highest differential gain (105 dB), followed by the Si TFET (96 dB) and the SiGe-source TFET (90 dB), with the MOSFET presenting the lowest gain (51 dB). However, the MOSFET has the best gain-bandwidth product (GBW) (9.2 MHz) followed by the Ge-source TFET (1.6 MHz), the SiGe-source TFET (900 kHz) and the Si TFET (41 kHz). The second group of OTAs, where the same power consumption was considered and where the gain of the MOSFET OTA and the GBW of the TFETs' circuits were increased was also studied. The gain of the MOSFET OTA increased to 56 dB, but it is still lower than the TFET circuits (96, 90 and 102 dB for the Si TFET, SiGe-source TFET and Ge-source TFET, respectively). The GBW of the Si TFET, SiGe-source TFET and Ge-source TFET circuits increased to 71 kHz, 1 MHz, and 2 MHz, respectively. Nevertheless, the MOSFET OTA has the best GBW (4.7 MHz) again but being just 2.35 times the GBW of the Ge-source TFET case. Therefore, because of the high gain of the TFETs OTAs, they are indicated for low power, low-frequency applications, with the Ge-source TFET presenting a good compromise between gain and GBW. The circuits' linearity was also verified, and they demonstrate to be more dependent on bias choices than on the devices themselves. Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil

Made available in DSpace on 2020-12-12T01:20:44Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-05-01 This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET's saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition. LSI/PSI/USP University of Sao Paulo Imec ClaRoo E.E. Dept KU Leuven Sao Paulo State University (UNESP) Sao Joao da Boa Vista Sao Paulo State University (UNESP) Sao Joao da Boa Vista

Made available in DSpace on 2020-12-12T01:26:49Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-01-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) This paper presents an evaluation of omega-gate nanowire n-and p-type SOI MOSFETs performance focusing on the main analog figures of merit, like saturation transcon-ductance (gmsat), output conductance (gD), transconductance over drain current (gm/IDS) ratio, Early voltage (VEA), intrinsic gain (AV) and unit gain frequency (ft). The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec), and in the worst case, a DIBL value smaller than 70 mV/V. Showing its immunity to short channel effects (SCEs) in the studied channel length range. The narrowest device showed great electrostatic coupling, improving gm, presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and In-ternet-of-Things (IoT). LSI/PSI/USP University of São Paulo UNESP São Paulo State University UNESP São Paulo State University

Made available in DSpace on 2020-12-12T01:25:28Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-01-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). It was shown that in-creasing source-to-drain separation from 25 nm to 45 nm re-duces output conductance degradation for high drain voltages but increases the saturation voltage in about 400 mV due to the increase in the inner resistance. Variation of 4nm in the pocket thickness, a major cause of device variability, resulted in a 50-fold reduction of the drain current, but the output conductance reaches the same value in all cases for sufficiently high Vds. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mir-rors, revealing that gate-source overlap of 3 nm decreases the minimum output voltage from 820 mV to 300 mV, in comparison with no misalignment and improves the analog characteristics of the Line-TFET by preventing output conductance degradation for high drain voltages. Simulations compared to ex-perimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. Simulations reveal that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on the design of a com-mon-source stage is shown by comparing with a MOSFET de-sign. This example shows that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET case. LSI/PSI/USP University of São Paulo UNESP Sao Paulo State University UNESP Sao Paulo State University

Made available in DSpace on 2019-10-06T15:48:43Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-05-01 This paper compares, for the first time, the total ionizing dose degradation of 600 keV proton-irradiated silicon triple gate SOI tunnel FETs (TFETs) with SOI FinFETs fabricated with the same structure on the same wafer. This work is based on electrical measurements and TCAD simulations. Devices with different dimensions were exposed up to 10 Mrad(Si) dose of proton radiation. For transistors with narrow fin width, the radiation influence is negligible in both devices types. For WFIN = 250 nm and a proton radiation dose up to 10 Mrad(Si), on the other hand, a severe influence is observed in nFinFETs and pFinFETs present on the same die as the p-type TFETs. In the TFETs, no marked influence is observed. Only for a TFET of WFIN = 500 nm and 10 Mrad(Si) one can observe some radiation influence. The main degradation is caused by the buried oxide positive fixed charges and the interface traps which was also confirmed by TCAD simulations. The tunneling current of Tunnel-FETs presents a much better radiation hardness compared to the drift-diffusion current of SOI FinFETs. Sao Paulo State University (UNESP) Campus Sao Joao da Boa Vista LSI/PSI/USP University of Sao Paulo ClaRoo Imec E.E. Dept KU Leuven Sao Paulo State University (UNESP) Campus Sao Joao da Boa Vista

Made available in DSpace on 2019-10-06T15:39:25Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-01-30 This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and -20 V for pMOS), the SS degrades from 61 mV dec -1 (W NW = 10 nm) to 68 mV dec -1 (W NW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (-20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec -1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones. LSI/PSI/USP University of Sao Paulo Faculdade de Tecnologia de Sao Paulo e Faculdade de Tecnologia de Osasco CEETEPS Sao Paulo State University (UNESP) Sao Joao da Boa Vista CEA LETI, Minatec Campus and University Grenoble Alpes Sao Paulo State University (UNESP) Sao Joao da Boa Vista

Made available in DSpace on 2019-10-06T15:56:07Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-01-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) The goal of this work is to analyze the effect of the drain to gate and to biomaterial alignments on n-type Tunnel-FET (nTFET) working like a permittivity based biosensor. The biomaterial over the drain and channel region influence through the different dielectric permittivity material (k, where ε = k∗ε0) in the sensing area. The results show that the use of Tunnel-FET ambipolar current presents high sensitivity for using it as biosensor devices (Bio-TFET) for transistors with the drain to gate underlap (LUD) of 27 nm and with minimum drain to biomaterial overlap (Lover = 0) region. LSI/PSI/USP University of Sao Paulo Sao Paulo State University (UNESP) Sao Paulo State University (UNESP)

Made available in DSpace on 2018-12-11T16:54:23Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-06-06 This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (A d), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest A d, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher A d and ON-state current than Point TFETs. LSI/PSI/USP University of Sao Paulo Sao Paulo State University (UNESP) Campus Sao Joao da Boa Vista Imec E.E. Department KU Leuven Sao Paulo State University (UNESP) Campus Sao Joao da Boa Vista

Made available in DSpace on 2018-12-11T16:45:10Z (GMT). No. of bitstreams: 0 Previous issue date: 2017-02-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) In this work the Line-TFET performance is compared with MOSFET and Point-TFET devices, with different architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. This analysis is based on the experimental basic analog parameters such as transconductance (gm), output conductance (gD) and intrinsic voltage gain (AV). Although the Line-TFETs present worse AV than the point-TFETs, when they are compared with MOSFET technology, the line-TFET shows a much better intrinsic voltage gain than both MOSFET architectures (FinFET and GAA). Besides the AV, the highest on-state current was obtained for Line-TFETs when compared with other two TFET architectures, which leads to a good compromise for analog application. LSI/PSI/USP – University of São Paulo, Av. Prof. Luciano Gualberto, trav. 3 no 158, 05508-010 Sao Paulo UNESP – Universidade Estadual Paulista, São João da Boa Vista imec, Kapeldreef 75 E.E. Dept KULeuven UNESP – Universidade Estadual Paulista, São João da Boa Vista

Made available in DSpace on 2018-12-11T16:44:23Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-10-13 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fonds Wetenschappelijk Onderzoek The effective hole mobility of long strained Ge pFinFETs, fabricated with shallow trench isolation (STI) first and last approaches, is systematically evaluated from room temperature down to 77 K, from planar-like (100 nm) to narrow (20 nm) devices. The goal is to identify the dominant scattering mechanism. Here, the split capacitance-voltage (CV) technique has been applied, based on combined current-voltage (I-V) and CV measurements. It is shown that even at 77 K, the phonon scattering mechanism dominates the STI last process, while the Coulomb scattering strongly affects the STI first approach. On the other hand, the latter shows slightly higher hole mobility compared to the STI last counterpart. LSI/PSI/USP University of Sao Paulo Imec Department of Solid State Sciences Ghent University UNESP Universidade Estadual Paulista EE Department KU Leuven UNESP Universidade Estadual Paulista

session: Reliability; International audience; Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi) are accurate, with error below 5%. At high temperature, the capacitance curves are narrower due to the threshold voltage (VT) lowering in n- and p-channels. However, the accuracy of tOX and tSi extraction is only marginally affected.

Made available in DSpace on 2018-11-26T15:31:25Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-10-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) FWO Logic IIAP Program An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation (Delta N) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. Univ Sao Paulo, BR-05508010 Sao Paulo, Brazil Katholieke Univ Leuven, B-3001 Leuven, Belgium IMEC, B-3001 Leuven, Belgium Univ Estadual Paulista, BR-13876750 Sao Joao Da Boa Vista, Brazil Natl Univ Singapore, Singapore 117575, Singapore Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium Univ Estadual Paulista, BR-13876750 Sao Joao Da Boa Vista, Brazil

Made available in DSpace on 2018-12-11T16:43:41Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-09-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) This letter characterizes the generation-recombination noise of Ge pFinFETs, for three different integration schemes: shallow trench isolation (STI) first strained devices; STI last for relaxed and strained ones. It is shown that many Lorentzians exhibit a VGS-independent and thermally activated characteristic frequency. This points out that the responsible defects are located inside the fin and they are found for all studied process conditions. One type of defect with a time constant value of 10 ms at room temperature is process-independent. Regarding the defects, their activation energies and hole capture cross sections have been extracted for fin widths varying from planar-like devices to narrow ones. It is shown that the STI last strained and relaxed devices yield a surface trap density three orders of magnitude above the typical value obtained for a blanket wafer. University of Sao Paulo Katholieke Universiteit Leuven Imec UNESP Department of Electrical Engineering Katholieke Universiteit Leuven UNESP CAPES: BEX 10537/14-7

session poster; International audience; Focusing on the channel length scalability, this paper analyzes the coupling coefficient (body factor) in thick (25nm) and thin (7nm) UTBB SOI devices. Experimental data and simulations demonstrate that the supercoupling effect further improves the device scalability and operation in thin silicon films. The impact of thinning the gate oxide and body on the inter-channel coupling is also documented.

This work presents an experimental analysis of the transconductance in vertical Ge source gate-all-around Tunnel-FETs for temperatures ranging from 100K to 400K. It was observed that the gm hump is related to the different conduction mechanisms which can be explained by the different temperature impact for each mechanism. This effect was also studied using numerical simulations.

session 1: Semiconductor Devices; International audience; This work aims to study the reliability of the Si film thickness extraction method based on the capacitance derivative analysis in p-i-n gated diodes. Results provided by the derivative procedure are compared to the basic capacitance method (without the derivative). The basic method yields accurate Si-film thicknesses, but it can only be applied to relatively thick body devices where the supercoupling effect does not occur. On the other hand, the use of the derivative analysis is feasible and effective in ultrathin devices. This makes the derivative procedure more suitable for the characterization of the body thickness in advanced FDSOI MOS-like devices.

An overview is given on the possibilities of using generation-recombination (GR) noise as a tool for defect spectroscopy in semiconductor materials and devices. The method is illustrated by n-channel MOSFETs fabricated on silicon-on-insulator (SOI) substrates with an ultra-thin buried oxide (UTBOX). As will be shown, the use of fully depleted (FD) UTBOX devices offers some unique opportunities and challenges. In the first instance, one can apply the standard GR noise spectroscopy in function of the temperature to derive the relevant deep-level parameters like the activation energy, the capture cross section and the concentration. In addition, some new type of spectroscopy can be applied to defects in the silicon film by exploiting the front- and/or back-gate bias dependence of the Lorentzian noise parameters. Finally, it is shown that for small geometry transistors the GR noise is generated by one or only a few centres. This becomes obvious in the time domain, where the channel current exhibits random telegraph signal (RTS) fluctuations. The up and down time constants and the relative RTS amplitude can be used to derive the GR centre parameters and, moreover, its spatial location, when combined with numerical device simulations. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

International audience; In this paper, UTBOX nMOSFETs with different gate dielectrics have been studied based on their lowfrequency noise (LFN) performance. Since LFN measurements have been successfully used as a characterization tool for determining the quality of the films, here, we have investigated the dielectric films used in state-of-the-art UTBOX devices in order to evaluate their performance and to identify the type of traps possibly introduced during the device processing. High-k gate dielectric devices have shown predominantly 1/f noise with a two-order of magnitude higher value than the conventional SiO2 ones which, consequently, results in higher density of traps in those devices. The carrier number fluctuations dominate the 1/f noise for both front and back interfaces. Due to the thin silicon film thickness there is a strong electrostatic coupling between front and back interfaces that interferes in the noise results as well as in transistor parameters. A contribution of the back interface noise source of about 14% on the measured noise in the front channel conduction was found, while the contribution of the front interface noise source is about 22% on the measured noise in the back channel conduction. The generation-recombination (GR) noise performed at different temperatures has enabled the identification of 6 types of traps and 2 unknown ones, being originated from the dry-etching or implantation damage.

International audience; The low-frequency (LF) noise behavior of Fully Depleted (FD) Ultra-Thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI) nMOSFETs is described from the perspective of the three major noise sources: 1/f-like or flicker noise, associated with carrier trapping/detrapping in the gate oxide; Generation-Recombination (GR) noise due to processing-induced defects in the thin silicon film and single-oxide-trap-related Random Telegraph Noise (RTN). It is shown that the fully depleted nature of the thin silicon films (

International audience; A low-frequency (LF) noise characterization of UTBOX SOI nMOSFETs is undertaken in order to understand the variation of the electron mobility in the front-channel. It is shown that there exists a reasonable correlation between the two parameters, which can be explained by Coulomb scattering at charged traps in the front and back-gate oxide. Exceptions to the observed trend are related to the presence of excess Generation- Recombination (GR) noise, associated with deep levels in the thin Si film.