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This study proposes a folded cascode CMOS low noise amplifier (LNA) with transformer feedback, implemented using a 0.13-μm CMOS process for wireless local area network front-end module applications. Compared to a conventional cascode inductive source degeneration LNA (ISDLNA), the folded cascode ISDLNA significantly improved the input-referred third-order intercept point (IIP3) as well as the 1-dB compression point (P1dB) by ensuring a large voltage headroom. Furthermore, the designed LNA also achieved a low noise figure (NF), while also saving the silicon area by magnetically coupling the source and folding inductors. When tested experimentally, the proposed LNA showed an S21 of 11.0 dB and an NF of 2.6 dB, while achieving an S11 of −7 dB at the operating frequency of 2.4 GHz. The measured input P1dB and IIP3 were −5.6 dBm and +2.5 dBm, respectively. The power dissipation was 9.6 mW from a 1.2-V supply voltage.

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

A CMOS up-conversion mixer with an intermediate frequency (IF) amplifier and local oscillator (LO) buffer is presented for mobile 28-GHz-band 5G dual-conversion transceivers. A balun transformer with improved common-mode rejection ratio characteristics is proposed to improve the LO second-harmonic signal suppression, which is a problem in the up-conversion mixer of the 5G dual-conversion architecture. By applying the proposed balun transformer instead of the conventional one, a common-mode rejection ratio greater than 10 dB can be achieved at the frequencies of the LO second-harmonic leakage signal. An up-conversion mixer with an IF amplifier and LO buffer incorporating the proposed balun transformer was implemented in a 65-nm CMOS process, and it draws a current of 31.4 mA from a 1-V supply voltage. It provides a gain larger than 22.2 dB, a noise figure less than 4.1 dB, a third-order output intercept point higher than 4.6 dBm, and an LO second-harmonic leakage signal lower than −55.5 dBm in frequencies ranging from 26.5 GHz to 29.5 GHz. It also exhibits a suppression improvement of the LO second-harmonic leakage signal of approximately 14 dB with respect to an up-conversion mixer with IF amplifier and LO buffer using the conventional balun transformer. The proposed up-mixer with IF amplifier and LO buffer is the first one reported that addresses the 2LO leakage issue and the first demonstration of 2LO leakage signal suppression improvement for a 5G mmWave dual-conversion single-quadrature transmitter.

This paper presents a highly efficient InGaP/GaAs HBT power amplifier (PA) implemented using a proposed high- $Q$ single- and two-winding transformer. A single- and two-winding transformer is designed with a printed circuit board (PCB) to combine the output power with a reduced passive loss. Compared to a typical 1:2 two-winding transformer, an additional unit amplifier is connected at the mid-point of the secondary winding to construct a single-winding transformer without additional windings. An IMD3 cancellation technique using a single- and two-winding transformer is also proposed to obtain a high linear output power with high power-added efficiency (PAE) without additional design circuitry. The IMD3 components of the two input currents in the single- and two-winding transformer are 180° out-of-phase cancelling each other at output. The proposed PA is integrated with an InGaP/GaAs HBT process using a PCB transformer. The experimental results demonstrate that the PA achieves a saturated output power of 33.3 dBm, with a PAE of 61.3% at 0.91 GHz. The proposed PA is also tested with an orthogonal frequency-division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signal having a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB at 0.91 GHz to evaluate the improvement in linearity. The PA achieves an adjacent channel leakage ratio (ACLR) of −42 dBc up to an output power of 26.0 dBm with a PAE of 26.8% and current consumption of 297 mA.

This paper presents a fully integrated linear power amplifier (PA) in a 65-nm CMOS process for mm-wave 5G applications. The proposed linear PA employs a compact symmetrical 4-way parallel–parallel power combiner with a third-order intermodulation distortion (IMD3) cancellation method to achieve high linear output power with a high power-added efficiency (PAE). An on-chip 4-way parallel–parallel power combiner, which combines the output power from 8-unit PAs, is designed with a compact footprint ( $241\,\,\mu \text{m}\,\,\times 241\,\,\mu \text{m}$ ). Conventional series power-combining transformer based power combiners have poor symmetrical performance for the amplitude and phase of the input impedance among unit PAs owing to the parasitic effects of the power combiners. However, the proposed parallel–parallel power combiner, which is based on parallel power-combining transformer structures, shows good symmetrical performances among unit PAs. Moreover, an IMD3 cancellation method using a parallel–parallel power combiner is proposed in this work. The proposed IMD3 cancellation method can support high-order modulation signals without increasing the complexity and reduce the dependence for digital predistortion (DPD). Consequently, the proposed linearization method obtains a high linear POUT and PAE without DPD. The PA in 65-nm CMOS demonstrates a saturated output power (PSAT) of 23.2 dBm, a 15.9-dB power gain, a 1-dB compressed output power ( $\text{P}_{\mathrm {O,1dB}}$ ) of 22 dBm, and a peak power-added efficiency (PAE) of 33.5% at 28 GHz. The measured error vector magnitude with 100 Msym/s of 256/512-QAM is −31.2/−32.1 dB with average output power of 18.02/17.73 dBm, average PAE of 17.6/16.1%, and adjacent channel power ratio (ACPR) of −30/−33.1 dBc without DPD. To the best of the authors’ knowledge, the proposed PA demonstrates high output power with the highest PAE performance supporting 256/512-QAM compared to the recently published fully integrated mm-wave 5G CMOS PAs.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-μm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 μm × 40 μm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 μW per pixel.

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. It is concluded that endless scaling of modern semiconductor technology has changed mobile hand-held radio system and service drastically during the past few years and it is shown that technology scaling helps continuously to design more smart systems in a less costly way.

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz. [ABSTRACT FROM AUTHOR]

In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabricated in 0.18 μm CMOS process are reported. These provide high-capacitance density of 2 fF/μm2 and 3.2 fF/μm2 and excellent dc and RF characteristics, respectively. The lumped circuit model of the stacked MIM capacitors is presented for high-frequency applications up to 20 GHz. The stacked MIM capacitors offer a reduced chip area for a given capacitance value and are expected to be a viable choice for integration of RF/mixed-mode circuits in a single chip. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1235–1238, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24305 [ABSTRACT FROM AUTHOR]

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-µm standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 µm² three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I²C master device such as universal I²C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm². This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications. [ABSTRACT FROM AUTHOR]

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-μm CMOS process. V-NPN has an inherently low flicker noise (1/ƒ noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-μm deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 μW from the 1.8-V supply. [ABSTRACT FROM AUTHOR]

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP2 than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP2,and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts. [ABSTRACT FROM AUTHOR]

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-pm CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology. [ABSTRACT FROM AUTHOR]

An experimental 2.4-GHz CMOS radio composed of RF and digital circuits for the low-power and low-rate preliminary IEEE802.15.4 WPAN is reported, consuming 21 mW in receive mode and 30 mW in transmit mode. The RF design focus is to maximize linearity for a given power consumption using linearization methods which lead an order of magnitude improvement in LNA/mixer IIP3/power performance. Chip-on-PCB technology allows implementation of a coin-sized radio at very low cost, which also provides 3 dBi gain patch antenna and high Q (>50) inductors. [ABSTRACT FROM AUTHOR]

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands. [ABSTRACT FROM PUBLISHER]

The testing of a monolithic bio-signal acquisition circuit with an analogue negative feedback loop for ubiquitous healthcare (u-healthcare) and the monitoring of physical activity is described. The large lowfrequency signal is effectively rejected by the proposed circuit, allowing the dynamic range of the more valuable signals to be improved. The proposed circuit has been designed and fabricated using a 0.18 μm 1-poly 6-metal CMOS process. Using an analogue negative feedback loop with a dual-gain filter, the proposed method provides an average signal-to-noise ratio 8.1 dB higher than that of the conventional method. [ABSTRACT FROM AUTHOR]

A new pixel circuit and driving method for large-area, high-luminance active matrix organic light-emitting diode (AMOLED) displays were studied to improve the image quality. The AMOLED display was designed with low-temperature poly-silicon thin film transistors (TFTs), which have good stability but poor uniformity. To overcome the uniformity problem, the proposed pixel circuit compensates for variations in the threshold voltage and the mobility of the driving TFT. The proposed pixel circuit can operate in two compensation modes for high-luminance operation; and the black data insertion was introduced to improve the characteristics of moving images. The pixel circuit was designed for an 11.6"WXGA top-emission AMOLED panel, and its non-uniformity was estimated to be < 4% with a mobility compensation time of 1 μs. [ABSTRACT FROM AUTHOR]