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The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal–oxide–semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (Vth) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions. [ABSTRACT FROM AUTHOR]

Floating-gate (FG)-type three-dimensional (3D) fin channel flash memories with triangular fin (TF) and rectangular fin (RF) channels and different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The electrical characteristics of the fabricated FG-type 3D fin channel flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 °C have been comparatively investigated. A higher P/E speed, a larger memory window, and a lower-voltage operation are experimentally obtained in the TF channel flash memories with an Al2O3–nitride–oxide (ANO) IPD layer (TF-ANO) than in the RF channel ones with the same ANO IPD layer (RF-ANO) and the TF channel ones with an oxide–nitride–oxide (ONO) IPD layer (TF-ONO). The larger memory window and lower-voltage operation of TF-ANO flash memories are due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF channels. It was also found that data retention for all fabricated FG-type 3D fin channel flash memories shows a weak dependence on temperature. [ABSTRACT FROM AUTHOR]

We have investigated the impact of heated ion implantation (I/I) on the performance and reliability of silicon-on-insulator (SOI) complementary metal–oxide–silicon (CMOS) fin field-effect transistors (FinFETs). An implantation temperature equal to and higher than 400 °C is needed to maintain the crystallinity of the Si substrate during I/I within the experimental conditions of ion species, implantation energy, and ion dose in this study. By heated I/I at 500 °C, the 11-nm-thick SOI layer perfectly maintains the crystallinity even after I/I, and a defect-free crystal is obtained by activation annealing. It was clarified that the cap layer is essential for the suppression of the out-diffusion during heated I/I. Heated I/I on the source and drain improves the on-current–off-current (Ion–Ioff), threshold voltage (Vth) variability, and bias temperature instability (BTI) characteristics of nMOS and pMOS FinFETs as compared with those after room-temperature I/I. [ABSTRACT FROM AUTHOR]

The impact of work function variation (WFV) in a metal gate (MG) electrode on low-frequency noise (LFN) is revealed for fin field-effect transistors (FinFETs). The LFN level is compared between the FinFETs having polycrystalline TiN and amorphous TaSiN MGs. The amorphous TaSiN MG exhibits a marked suppression of flicker noise in comparison with the TiN MG. The difference in the LFN level is correlated with the threshold voltage variability reflecting the WFV of the MG. By modeling the WFV of the TiN MG in the FinFET structure by three-dimensional device simulation, we clearly reveal the mechanism of the LFN increase by the WFV. [ABSTRACT FROM AUTHOR]