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High-performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (\(L_{ch}\)) down to 20 nm are fabricated by integrating a higher-k \(LaAlO_3\)-based gate-stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5 nm) \(Al_2O_3\) interfacial layer between the higher k \(LaAlO_3\) and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63 mV/dec is demonstrated at sub-80-nm \(L_{ch}\) for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors., Chemistry and Chemical Biology

InGaAs gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6 nm nanowire thickness have been experimentally demonstrated at sub-80 nm channel length. The effects of forming gas anneal (FGA) on the performance of these devices have been systematically studied. The 30 min \(400^{\circ}C\) FGA \((4\%H_2/96\%N_2)\) is found to improve the quality of the \(Al_2O_3/InGaAs\) interface, resulting in a subthreshold slope reduction over 20 mV/dec (from 117 mV/dec in average to 93 mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate electrostatic control. With the FGA passivation and the ultra-thin nanowire structure, InGaAs MOSFETs are promising for future logic applications., Chemistry and Chemical Biology

InGaAs gate-all-around nanowire MOSFETs with channel length down to 50 nm have been experimentally demonstrated by a top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance, and effective mobility due to stronger quantum confinement and the volume-inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume-inversion effect appears at a larger dimension for InGaAs nanowire MOSFET than its Si counterpart. [ABSTRACT FROM AUTHOR]

We have systematically studied the passivation of InP (100) and (111)A substrate using atomic-layer-deposited Al2O3 as gate dielectric. Modified high- and low-frequency method and full conductance method has been applied to evaluate the interface trap density (Dit) distribution at Al2O3/InP interface through MOS capacitor (MOSCAP) and MOSFET measurements. Lower Dit towards conduction band is obtained from (111)A surface, accompanied by an increase in midgap Dit. This leads to the demonstration of record-high drive current (Ids=600 μA/μm) for a InP (111)A NMOSFET with gate length (LG) of 1 μm and relatively large subthreshold swing of 230 mV/dec at off-state. Detailed DC IV and current drift measurements confirm the trap distribution from capacitance-voltage characterization. A trap neutral level (E0) model is proposed to explain all observations from MOSCAP and MOSFET characterizations. A universal behavior of the E0 shift on III-V (111)A surface is also analyzed and this observation can play a pivotal role in interface engineering for future III-V CMOS technology with 3D structures. [ABSTRACT FROM AUTHOR]