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Today, electronics are implemented on rigid substrates. However, many objects in daily-life are not rigid — they are bendable, stretchable and even foldable. Examples are paper, tapes, our body, our skin and textiles. Until today there is a big gap between electronics and bendable daily-life items. Concerning this matter, the DFG Priority Program FFlexCom aims at paving the way for a novel research area: Wireless communication systems fully integrated on an ultra-thin, bendable and flexible piece of plastic or paper. The Program encompasses 13 projects led by 25 professors. By flexibility we refer to mechanical flexibility, which can come in flavors of bendability, foldability and, stretchability. In the last years the speed of flexible devices has massively been improved. However, to enable functional flexible systems and operation frequencies up to the sub-GHz range, the speed of flexible devices must still be increased by several orders of magnitude requiring novel system and circuit architectures, component concepts, technologies and materials.

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm−1.

We apply molecular beam epitaxy to grow GeSn-nanoparticles on top of Si-nanopillars patterned onto p-type Si wafers. We use X-ray photoelectron spectroscopy to confirm a metallic behavior of the nanoparticle surface due to partial Sn segregation as well as the presence of a superficial Ge oxide. We report the observation of stable field emission current from the GeSn-nanoparticles. We prove that field emission can be enhanced by preventing GeSn nanoparticles oxidation or by breaking the oxide layer through electrical stress. Finally, we show that GeSn/p-Si junctions have a rectifying behavior., Comment: Research paper. 7 pages, 4 figures

Integration of graphene with Si microelectronics is very appealing by offering potentially a broad range of new functionalities. New materials to be integrated with Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etch and electrochemical delamination methods with respect to residual sub-monolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection x-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10$^{13}$ atoms/cm$^{2}$. These metal impurities appear to be partly mobile upon thermal treatment as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics these results reveal that further progress in synthesis, handling, and cleaning of graphene is required on the way to its advanced electronic and optoelectronic applications., 26 pages, including supporting information

Among the many anticipated applications of graphene, some - such as transistors for Si microelectronics - would greatly benefit from the possibility to deposit graphene directly on a semiconductor grown on a Si wafer. We report that Ge(001) layers on Si(001) wafers can be uniformly covered with graphene at temperatures between 800{\deg}C and the melting temperature of Ge. The graphene is closed, with sheet resistivity strongly decreasing with growth temperature, weakly decreasing with the amount of deposited C, and reaching down to 2 kOhm/sq. Activation energy of surface roughness is low (about 0.66 eV) and constant throughout the range of temperatures in which graphene is formed. Density functional theory calculations indicate that the major physical processes affecting the growth are: (1) substitution of Ge in surface dimers by C, (2) interaction between C clusters and Ge monomers, and (3) formation of chemical bonds between graphene edge and Ge(001), and that the processes 1 and 2 are surpassed by CH$_{2}$ surface diffusion when the C atoms are delivered from CH$_{4}$. The results of this study indicate that graphene can be produced directly at the active region of the transistor in a process compatible with the Si technology.

In this work, we propose an integration approach for double gate graphene field effect transis- tors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The com- plete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bend- ing in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Despite exceptional intrinsic properties of graphene, field effect transistors with graphene channels (GFETs) are limited by the absence of an electronic band gap. The resulting low ION-IOFF ratio and low output resistance makes GFETs unsuitable for logic applications [1] and limits radio frequency (RF) applications [2]. We will present a graphene-based electronic device in which the 0 eV band gap does not limit the device performance: a hot electron transistor (HET) with a graphene base (Graphene Base Transistor, GBT) [3,4]. The single-atomic thinness and high conductivity are decisive advantages of a graphene base [5]. Here, we report on the fabrication and full DC-characterization of GBTs with high ION-IOFF ratio of 105.

We study the contact resistance and the transfer characteristics of back-gated field effect transistors of mono- and bi-layer graphene. We measure specific contact resistivity of ~ 7 k Ω μm 2 and ~ 30k Ω μm 2 for Ni and Ti, respectively. We show that the contact resistance is a significant contributor to the total source-to-drain resistance and it is modulated by the back-gate voltage. We measure transfer characteristics showing a double dip feature that we explain as the effect of doping due to charge transfer from the contacts causing minimum density of states for graphene under the contacts and in the channel at different gate voltage.

We present a novel, graphene-based device concept for high-frequency operation: a hot electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows THz operation. Based on energy band considerations we propose a specific materials solution that is compatible with SiGe process lines., 9 pages, 3 figures; IEEE Electron Device Letters, Vol.33, Issue 5, (2012)

We report the observation and characterization of field emission current from individual single- and few-layer graphene flakes laid on a flat SiO2/Si substrate. Measurements were performed in a scanning electron microscope chamber equipped with nanoprobes, used as electrodes to realize local measurements of the field emission current. We achieved field emission currents up to 1 {\mu}A from the flat part of graphene flakes at applied fields of few hundred V/{\mu}m. We found that emission process is stable over a period of several hours and that it is well described by a Fowler-Nordheim model for currents over 5 orders of magnitude.

We discuss the origin of an additional dip other than the charge neutrality point observed in the transfer characteristics of graphene-based field-effect transistors with a Si/SiO2 substrate used as the back-gate. The double dip is proved to arise from charge transfer between the graphene and the metal electrodes, while charge storage at the graphene/SiO2 interface can make it more evident. Considering a different Fermi energy from the neutrality point along the channel and partial charge pinning at the contacts, we propose a model which explains all the features observed in the gate voltage loops. We finally show that the double dip enhanced hysteresis in the transfer characteristics can be exploited to realize graphene-based memory devices.