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In the near future, Exascale systems will need to bridge three technology gaps to achieve high performance while remaining under tight power constraints: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetic; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA addresses these gaps through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research. This work is supported by the TEXTAROSSA project (G.A. n. 956831), as part of the EuroHPC initiative. Peer Reviewed Article signat per 56 autors/es: Giovanni Agosta (a) , Marco Aldinucci (f) , Carlos Alvarez (h) , Roberto Ammendola (n) , Yasir Arfat (f) , Olivier Beaumont (g) , Massimo Bernaschi (c) , Andrea Biagioni (j) , Tommaso Boccali (l) , Berenger Bramas (g) , Carlo Brandolese (a) , Barbara Cantalupo (f) , Mauro Carrozzo (c) , Daniele Cattaneo (a) , Alessandro Celestini (c) , Massimo Celino (b) , Iacopo Colonnelli (f) , Paolo Cretaro (j) , Pasqua D’Ambra (d) , Marco Danelutto (e) , Roberto Esposito (f) , Lionel Eyraud-Dubois (g) , Antonio Filgueras (h) , William Fornaciari (a) , Ottorino Frezza (j) , Andrea Galimberti (a) , Francesco Giacomini (k) , Brice Goglin (g) , Daniele Gregori (o) , Abdou Guermouche (g) , Francesco Iannone (b) , Michal Kulczewski (i) , Francesca Lo Cicero (j) , Alessandro Lonardo (j) , Alberto R. Martinelli (f) , Michele Martinelli (j) , Xavier Martorell (h) , Giuseppe Massari (a) , Simone Montangero (m), Gianluca Mittone (f) , Raymond Namyst (g) , Ariel Oleksiak (i) , Paolo Palazzari (b) , Pier Stanislao Paolucci (j) , Federico Reghenzani (a)∗ , Cristian Rossi (j) , Sergio Saponara (e) , Francesco Simula (j) , Federico Terraneo (a) , Samuel Thibault (g) , Massimo Torquati (e) , Matteo Turisini (j) , Piero Vicini (j) , Miquel Vidal (h) , Davide Zoni (a) , Giuseppe Zummo (b) // (a) Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Italy; (b) ENEA, Agenzia nazionale per le nuove tecnologie, l’energia e lo sviluppo economico sostenibile, Italy; (c) Istituto per le Applicazioni del Calcolo (IAC), Consiglio Nazionale delle Ricerche, Rome, Italy; (d) Istituto per le Applicazioni del Calcolo (IAC), Consiglio Nazionale delle Ricerche, Naples, Italy; (e) University of Pisa, Italy; (f) University of Torino, Italy; (g) Institut national de recherche en informatique et en automatique (Inria), France; (h) Barcelona Supercomputing Center, Spain; (i) Poznan Supercomputing and Networking Center, Poland; (j) Istituto Nazionale di Fisica Nucleare, Sezione di Roma, Italy; (k) Istituto Nazionale di Fisica Nucleare, CNAF, Italy; (l) Istituto Nazionale di Fisica Nucleare, Sezione di Pisa, Italy; (m) University of Padova and Istituto Nazionale di Fisica Nucleare Sezione di Padova, Italy; (n) Istituto Nazionale di Fisica Nucleare, Sezione di Roma Tor Vergata, Italy; (o) E4 Computer Engineering Spa, Italy

To achieve high performance and high energy efficiency on near-future exascale computing systems, three key technology gaps needs to be bridged. These gaps include: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetics; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA aims at tackling this gap through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models and tools derived from European research. This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative. Peer Reviewed Article signat per 51 autors/es: Giovanni Agosta, Daniele Cattaneo, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese (DEIB – Politecnico di Milano, Italy, name.surname@polimi.it) | Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo (ENEA, Italy, name.surname@enea.it) | Massimo Bernaschi, Pasqua D’Ambra (Istituto per le Applicazioni del Calcolo (IAC) - CNR, Italy, name.surname@cnr.it) | Sergio Saponara, Marco Danelutto, Massimo Torquati (University of Pisa, Italy, name.surname@unipi.it) | Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto R. Martinelli, Gianluca Mittone (University of Torino, Italy, name.surname@unito.it) | Olivier Beaumont, Berenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault (Inria - France, name.surname@inria.fr) | Antonio Filgueras, Miquel Vidal, Carlos Alvarez, Xavier Martorell (BSC - Spain, name.surname@bsc.es) | Ariel Oleksiak, Michal Kulczewski (PSNC, Poland, ariel@man.poznan.pl, kulka@man.poznan.pl) | Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini (INFN Sezione di Roma - Italy, name.surname@roma1.infn.it) | Francesco Giacomini (INFN CNAF - Italy, name.surname@cnaf.infn.it) | Tommaso Boccali (INFN Sezione di Pisa - Italy, name.surname@pi.infn.it) | Simone Montangero (University of Padova and INFN Sezione di Padova - Italy, name.surname@pd.infn.it) | Roberto Ammendola (INFN Sezione di Roma Tor Vergata - Italy, name.surname@roma2.infn.it)

[EN] Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due to the exponential increase in the number of devices per chip, to higher system fault rates. Consequently, High-performance Computing (HPC) systems need to integrate prediction, detection, and recovery mechanisms to cope with faults efficiently. This article reviews fault detection, fault prediction, and recovery techniques in HPC systems, from electronics to system level. We analyze their strengths and limitations. Finally, we identify the promising paths to meet the reliability levels of Exascale systems., This work has received funding from the European Union's Horizon 2020 (H2020) research and innovation program under the FET-HPC Grant Agreement No. 801137 (RECIPE). Jaume Abella was also partially supported by the Ministry of Economy and Competitiveness of Spain under Contract No. TIN2015-65316-P and under Ramon y Cajal Postdoctoral Fellowship No. RYC-2013-14717, as well as by the HiPEAC Network of Excellence. Ramon Canal is partially supported by the Generalitat de Catalunya under Contract No. 2017SGR0962.

The current trends in Internet of Things (IoT) lead to the deployment of low-power devices covering a wide range of application scenarios. These devices have the goal of executing simple tasks, automatically, usually with strict requirements in terms of space and cost. Typically, these devices have to rely on batteries or by harvesting energy devices (e.g., solar panels), in order to operate. On the other hand, IoT devices may be equipped with powerful multi-core CPUs to achieve performance goals, making the management of the energy budget a challenging task. This requires the development of an effective management system, that takes into account current and future energy budget availability, to dynamically bound the actual allocation of processing resources. Specifically, when exploiting solar panels for power supply, we can leverage on the weather forecast, to estimate the availability of energy in the near future. This paper introduces a predictive energy budget management system, targeting multi-core based embedded platforms. Thanks to both local and large-scale weather information, our solution aims at predicting the future incoming power and, accordingly, tuning the exploitable performance level to keep the system running under any environmental condition.

Achieving an optimal management of the energy budget of mobile devices, while matching the applications performance requirements is always a challenging task. In our research, we are exploring the possible benefits of driving run-time management strategies, from an application perspective, by integrating the programming model with the run-time system and exploiting suitable API for explicit application requirements specification.

High-Performance Computing (HPC) is rapidly moving towards the adoption of nodes characterized by an heterogeneous set of processing resources. This has already shown benefits in terms of both performance and energy efficiency. On the other side, heterogeneous systems are challenging from the application development and the resource management perspective. In this work, we discuss some outcomes of the MANGO project, showing the results of the execution of real applications on a emulated deeply heterogeneous systems for HPC. Moreover, we assessed the achievements of a proposed resource allocation policy, aiming at identifying a priori the best resource allocation options for a starting application.

In battery-powered embedded systems, the energy budget management is a critical aspect. For systems using unreliable power sources, e.g. solar panels, the continuous system operation is a challenging requirement. In such scenarios, effective management policies must rely on accurate energy estimations. In this paper we propose a measurement-based probabilistic approach to address the worst-case energy consumption (WCEC) estimation, coupled with a job admission algorithm for energy-constrained task scheduling. The overall goal is to demonstrate how the proposed approach can introduce benefits also in mission-critical systems, where unsafe energy budget estimations cannot be tolerated.

The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors.

Dynamic Voltage and Frequency Scaling (DVFS) is the preferred actuator for power-performance policies, and its use is growing also for thermal management. DVFS implementations, especially for embedded platforms, have historically provided only few possible operating points, despite this may impair the optimality of the frequency selection for a given application. Moreover, with multiple policies making use of it, the rate at which frequency and voltage changes will occur in a given system is expected to increase. The work presented in this paper has a two-fold objective: first, to present a methodology to extend a DVFS driver with additional operating points and second, to measure the impact of DVFS transitions from the performance and energy consumption perspective. This contribution can thus help both operating system and run-time manager designers to implement more efficient policies, as well as device driver programmers and hardware designers to optimize the DVFS infrastructure. The proposed approach has been tested on a quad-core ARM Cortex-A9 CPU based development board.

[EN] The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated., This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668.

This article is centred on a mathematical weather forecasting model that must run regularly (i.e. 24/7) on an HPC system. Depending on the environmental conditions, each execution of the model may have a different deadline and a different accuracy requirement. In order to minimize power consumption and heat, we minimize resource allocation as far as the deadlines allow, thus evenly spreading resource usage over time while nonetheless complying with the deadlines. Our work relies on a run-time resource manager that adapts resource allocation to the runtime-variable performance demand of applications. The resource assignment is temperature-aware: the application is dynamically migrated on the coolest cores, and this has a positive impact on the system reliability.

The increasing interest in the integration of Mixed Criticality Systems (MCS) in Commercial-Off-The-Shelf (COTS) platforms leads to an increasing number of challenges. The possibility of sharing computing resources among applications with different time criticalities is a key goal for COTS systems, but still hard to achieve. Classical approaches in real-time systems are not feasible when platform and operating system may introduce unpredictability in the task execution. Moreover, if the system must also meet non-functional requirements (e.g., thermal and power management), dynamic approaches of computing resources allocation are more effective than static ones. Unfortunately, this contributes to increasing the complexity of the scenario. In MCS, the overheads and the unpredictability caused by sharing resources like cache memories have been well studied. However, in some cases we could also consider the operating system itself as a potential source of unexpected and unpredictable latencies, if several running tasks perform system calls. This work aims at proposing a model for the intra-core and inter-core interferences and the analysis of the OS-induced latencies in a Linux real-time system, both essential for the creation of smart and effective run-time resource management policies.

The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated.

In the latest years, we observed an exponential growth of the market of the mobile devices. In this scenario, it assumes a particular relevance the rate at which mobile devices are replaced. According to the International Telecommunicaton Union in fact, smart-phone owners replace their device every 20 months, on average. The side effect of this trend is to deal with the disposal of an increasing amount of electronic devices which, in many cases, arestill working. We believe that it is feasible to recover such an unexploited computational power. Through a change of paradigm in fact, it is possible to achieve a two-fold objective: 1) extend the mobile devices lifetime, 2) enable a new opportunity to speed up mobile applications. In this paper we aim at providing a survey of state-of-art solutions aim at going in the direction of a Distributed Mobile Computing paradigm. We put in evidence the challenges to be addressed in order to implement this paradigm and we propose some possible future improvements.

This paper introduces the mig framework: an Open MPI extension to transparently support the migration of application processes, over different nodes of a distributed High-Performance Computing (HPC) system. The framework provides mechanism on top of which suitable resource managers can implement policies to react to hardware faults, address performance variability, improve resource utilization, perform a fine-grained load balancing and power thermal management. Compared to other state-of-the-art approaches, the mig framework does not require changes in the application code. Moreover, it is highly maintainable, since it is mainly a self-contained solution that has required a very few changes in other already existing Open MPI frameworks. Experimental results have shown that the proposed extension does not introduce significant overhead in the application execution, while the penalty due to performing a migration can be properly taken into account by a resource manager.

In this paper, we provide an overview of the MANGO project and its goal. The MANGO project aims at addressing power, performance and predictability (the PPP space) in future High-Performance Computing systems. It starts from the fundamental intuition that effective techniques for all three goals ultimately rely on customization to adapt the computing resources to reach the desired Quality of Service (QoS). From this starting point, MANGO will explore different but interrelated mechanisms at various architectural levels, as well as at the level of the system software. In particular, to explore a new positioning across the PPP space, MANGO will investigate system-wide, holistic, proactive thermal and power management aimed at extreme-scale energy efficiency., This project has received funding from the the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671668.

The technology scaling towards the 10nm of the silicon manufacturing, is going to introduce variability challenges, mainly due to the growing susceptibility to thermal hot-spots and time-dependent variations (aging) in the silicon chip. The consequences are two-fold: a) unpredictable performance, b) unreliable computing resources. The goal of the HARPA project is to enable next-generation embedded and high-performance heterogeneous many-core processors to effectively address this issues, through a cross-layer approach, involving several component of the system stack. Each component acts at different levels and time granularity. This paper focus on one of the components of the HARPA stack, the HARPA-OS, showing early results of a first integration step of the HARPA approach in a real High-Performance Computing (HPC) application scenario.

Since the silicon technology entered the many-core era, new computing platforms are exploiting higher and higher levels of parallelism. Thanks to scalable, clustered architectures, embedded systems and high-performance computing (HPC) are rapidly converging.We are also experiencing a rapid overlapping of the challenges related to efficient exploitation of processing resources. Platform-specific optimization and application boosting cannot be considered independently anymore. Thus the increased interest towards broader and versatile methodologies, which could easily scale from the embedded up to the general-purpose domain.

To support adaptivity of data parallel applications on multi-core platforms, we propose a framework based on the combination of OpenCL application auto-tuning and run-time resource management. The framework addresses computationally intensive multimedia OpenCL applications. For these target applications, we show that application auto-tuning, based on design-time analysis, can become synergistic with run-time resource management. In the proposed framework, run-time decisions are taken by each application, autonomously, to achieve system adaptivity. This paper describes the methodology and related toolchain, defined during the 2PARMA European project, based on the integration of independent tools to provide effective compilation of OpenCL code, multi-objective design space exploration, application monitoring and tuning and system-wide run-time resource management. Experimental results are reported for design optimization of an OpenCL stereo-matching application and then for a resource contention scenario where multiple stereo-matching applications are executed on the same platform with different run-time requirements.

Mainstream multicore architectures allow the execution of mixed workloads where multiple parallel applications run concurrently competing on shared computational resources. As different applications exhibit different and time varying resources needs, a suitable allocation policy is required to properly select and map resources at run-time on demanding applications.We demonstrate how a user-space run-time resource manager could be extended to easily take advantage of performance counters in order to optimize both workloads execution time and energy consumption. Our approach, initially evaluated on a quad-core Intel machine considering a representative set of mixed-workloads from a standard benchmark suite, attains a 49,9% mean energy-delay-product (EDP) speed-up over the standard Linux case, and a 13.4% EDP speed-up over our previous work.

The transition to Exascale computing is going to be characterised by an increased range of application classes. In addition to traditional massively parallel "number crunching" applications, new classes are emerging such as real-time HPC and data-intensive scalable computing. Furthermore, Exascale computing is characterised by a "democratisation" of HPC: to fully exploit the capabilities of Exascale-level facilities, HPC is moving towards enabling access to its resources to a wider range of new players, including SMEs, through cloud-based approaches [1]. Finally, the need for much higher energy efficiency is pushing towards deep heterogeneity, widening the range of options for acceleration, moving from the traditional CPU-only organization, to the CPU plus GPU which currently dominates the Green5001, to more complex options including programmable accelerators and even (reconfigurable) hardware accelerators [2].