Search

Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate., Submitted to IEEE QCE 2023

We introduce a novel approach to translate arbitrary 3-SAT instances to Quadratic Unconstrained Binary Optimization (QUBO) as they are used by quantum annealing (QA) or the quantum approximate optimization algorithm (QAOA). Our approach requires fewer couplings and fewer physical qubits than the current state-of-the-art, which results in higher solution quality. We verified the practical applicability of the approach by testing it on a D-Wave quantum annealer.

In most qubit realizations, prototype devices are available and are already utilized in both industry and academic research. Despite being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed for enabling successful algorithm executions during the NISQ era, targeting mostly technologies with high qubit counts. Not so much attention has been paid to the implementation of compilation methods for quantum processors based on spin-qubits due to the scarce availability of current experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring quantum circuit mapping solutions for these spin-qubit devices. In this work, we discuss the unique mapping challenges of a scalable spin-qubit crossbar architecture with shared control [arXiv:1711.03807] and introduce $\textit{SpinQ}$, the first native compilation framework for scalable spin-qubit architectures that maps quantum algorithms on this crossbar architecture. At the core of $\textit{SpinQ}$ is the $\textit{Integrated Strategy}$ that addresses the unique operational constraints of the crossbar while considering compilation (execution time) scalability, having a $O(n)$ computational complexity. To evaluate the performance of $\textit{SpinQ}$ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping technique improvements for the crossbar architecture that could increase algorithm success rates and potentially inspire further research on quantum circuit mapping techniques for other scalable spin-qubit architectures., 18 pages, 16 figures

Quantum circuits are widely used for benchmarking quantum computers and therefore crucial for the development and improvement of full-stack quantum computing systems. To execute such circuits on a given quantum processor, they have to be modified to comply with its physical constraints. That process is done during the compilation phase and known as mapping of quantum circuits. The result of the mapping procedure is highly dependent not only on the hardware constraints, but also on the properties of the circuit itself. In this paper, we propose to explore the structure of quantum circuits to get detailed insights into their success rate when being executed on a given quantum device while using a specific compilation technique. To this purpose, we have characterized a large body of quantum circuits by extracting graph theory-based properties from their corresponding qubit interaction graphs and afterwards clustered them based on those and other commonly used circuit-describing parameters. This characterization will help i) to perform an in-depth analysis of quantum circuits and their structure and group them based on similarities; ii) to better understand and compare the mapping performance when run on a quantum processor and, later on, iii) to develop mapping techniques that use information from both, algorithms and quantum devices. Our simulation results show a clear correlation between interaction graph-based parameters as well as clusters of circuits with their mapping performance metrics when considering the constraints of a Surface-97 processor, as well as of IBM-53 Rochester and Aspen-16 devices. In addition to that, we provide an up-to-date collection of quantum circuits and algorithms taken from well-known sources with the goal of having an all-gathering, easy-to-use, categorized and characterized benchmark set available for the quantum computing community.

We introduce Q-Nash, a quantum annealing algorithm for the NP-complete problem of finding pure Nash equilibria in graphical games. The algorithm consists of two phases. The first phase determines all combinations of best response strategies for each player using classical computation. The second phase finds pure Nash equilibria using a quantum annealing device by mapping the computed combinations to a quadratic unconstrained binary optimization formulation based on the Set Cover problem. We empirically evaluate Q-Nash on D-Wave’s Quantum Annealer 2000Q using different graphical game topologies. The results with respect to solution quality and computing time are compared to a Brute Force algorithm and the Iterated Best Response heuristic.

The efficiency of Quantum Characterisation, Verification, and Validation (QCVV) protocols highly hinges on the agreement between the assumed noise model and the underlying error mechanisms. As a matter of fact, errors in Quantum Processing Units (QPUs) incorporate various aspects of context-dependability which are overlooked by the majority of the commonly used QCVV protocols. As QCVV protocols are indispensable when it comes to characterizing and evaluating quantum operations, there is a serious need for a detailed characterization taking into account such aspects. In this work, we address these shortcomings by designing a context-aware version of the gate set tomography (GST) protocol. Our experiment selection approach is based on a polynomial quantification of the accumulation of errors within the designed circuits. Using simulated QPUs, we show that this technique enables a characterization with an inaccuracy reaching $10^{-5}$. Furthermore, we use our proposed protocol to experimentally infer context-dependent errors, namely crosstalk and memory effects, in a publicly accessible cloud-based superconducting qubits platform. Our results show that when the GST is upgraded to include such features of context-awareness, a large coherence in the errors is observed. These findings open up possibilities of drastically reducing the errors within the currently demonstrated QPUs.

We introduce Q-Nash, a quantum annealing algorithm for the NP-complete problem of Fnding pure Nash equilibria in graphical games. The algorithm consists of two phases. The first phase determines all combinations of best response strategies for each player using classical computation. The second phase finds pure Nash equilibria using a quantum annealing device by mapping the computed combinations to a quadratic unconstrained binary optimization formulation based on the Set Cover problem. We empirically evaluate Q-Nash on D-Wave's Quantum Annealer 2000Q using different graphical game topologies. The results with respect to solution quality and computing time are compared to a Brute Force algorithm and the Iterated Best Response heuristic.

When solving propositional logic satisfiability (specifically 3SAT) using quantum annealing, we analyze the effect the difficulty of different instances of the problem has on the quality of the answer returned by the quantum annealer. A high-quality response from the annealer in this case is defined by a high percentage of correct solutions among the returned answers. We show that the phase transition regarding the computational complexity of the problem, which is well-known to occur for 3SAT on classical machines (where it causes a detrimental increase in runtime), persists in some form (but possibly to a lesser extent) for quantum annealing., 13 pages, published at QTOP 2019

In this work, we consider the following problem: given a graph, the addition of which single edge minimises the effective graph resistance of the resulting (or, augmented) graph. A graph’s effective graph resistance is inversely proportional to its robustness, which means the graph augmentation problem is relevant to, in particular, applications involving the robustness and augmentation of complex networks. On a classical computer, the best known algorithm for a graph with N vertices has time complexity (Formula Presented). We show that it is possible to do better: Dürr and Høyer’s quantum algorithm solves the problem in time (Formula Presented). We conclude with a simulation of the algorithm and solve ten small instances of the graph augmentation problem on the Quantum Inspire quantum computing platform.

Quantum Software Engineering (QSE) is a recent trend - focused on unifying the principles of quantum mechanics and practices of software engineering - to design, develop, validate, and evolve quantum age software systems and applications. Software architecture for quantum computing (a.k. a. quantum software architectures (QSA)) supports the design, development, and maintenance etc. phases of quantum software systems using architectural components and connectors. QSA can enable quantum software designers and developers to map the operations of Qubits to architectural components and connectors for implementing quantum software. This research aims to explore the role of QSAs by investigating (i) architectural process having architecting activities, and (ii) human roles that can exploit available tools to automate and customise architecture-centric implementation of quantum software. Results of this research can facilitate knowledge transfer, enabling researchers and practitioners, to address challenges of architecture-centric implementation of quantum software systems. peerReviewed