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Purpose This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor. Design/methodology/approach The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established. Findings After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation. Originality/value An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

This paper focuses on the time-domain analysis of bandpass (BP) negative group delay (NGD) function. The innovative NGD investigation is based on the time-domain experimentation of an innovative topology of “lill”-shape passive microstrip circuit. The design principle of the proof of concept (POC) constituted by particular microstrip shapes is described. The NGD circuit is inspired from a recent fully distributed “li”-topology. Before the time-domain investigation, the BP NGD specifications of the circuit under study are academically defined. As practical application of the basic definition, a frequency domain validation of “lill”-circuit is presented in the first section of the paper. The POC circuit is specified by a -8 ns NGD value at 2.31 GHz NGD center frequency and a 27 MHz NGD bandwidth. The “lill”-circuit exhibits an attenuation loss of about -6.2 dB at the NGD center frequency. Then, the two-port black box model of “lill”-NGD-circuit represented by touchstone data of the measured S-parameters is exploited for the transient simulation. The measured group delay (GD) illustrates that the tested “lill”-circuit operates as a BP function regarding the NGD with NGD equal to -8.1 ns at the NGD center frequency. The time-domain demonstration of the BP NGD function was performed using a gaussian pulse modulating sine carrier. The innovative experimental setup with the possibility to plot simultaneously well synchronized input and output signals is explained. The BP NGD time-domain response is understood from commercial tool simulation using the touchstone S-parameters of the measured “lill”-circuit by using a Gaussian up-converted pulse having a 27 MHz frequency bandwidth. It was observed that the output signals are delayed when the sine carrier is out of NGD-band. However, the output signal envelope is in advanced of about -8 ns when the carrier is tuned to be approximately equal to the 2.31 GHz NGD center frequency. To confirm the time-domain typical behavior of BP NGD response, an input pulse signal having Gaussian waveform were considered during the test. However, the input signal spectrum must be determined in function of the NGD bandwidth. After tests, measured output signal envelopes presenting leading edge, trailing edge and peak in time-advance compared to the input ones are observed experimentally. The results of the present feasibility study open a potential microwave communication application of BP NGD function notably for systems operating with ISM and IEEE 802.11 standards.

International audience; Most of the negative group delay (NGD) circuit recent investigation were focused on the classes of lowpass and bandpass categories. Few research works are currently available in the literature on the typical high-pass (HP) NGD function. This paper introduces an original HP-NGD circuit theory of four-port passive topology constituted by a single lumped capacitor. The S-matrix equivalent model of the innovative topology is established from the admittance matrix. Then, the basic frequency analytical responses are expressed. Then, the GD model is derived in function of the capacitor. It was found analytically that the four-port mono-capacitor passive circuit is susceptible to behave originally as an unfamiliar HP-NGD function. An innovative HP-NGD analysis is explored in addition to the expression of synthesis design equation in function of the expected NGD cutoff frequency which is linked to NGD optimal value. The validity of the established HP-NGD circuit theory is verified with a proof of concept (POC). As expected, the HP-NGD behavior showing a good correlation between analytical model and simulation is obtained.

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A transient study of bandpass (BP) negative group delay (NGD) function is devoted in this paper. The transient analysis is applied to an original topology of NGD barcode-shape microstrip circuit. The performed investigation explains how to realize the transient analysis of tri-band NGD circuit. The time-domain (TD) parametrization of the test is established from the BP-NGD specifications of the circuit under test (CUT) based on the S-parameter model. The input signal is a Gaussian pulse characterized in function of the NGD bandwidth (BW) and center frequency. The feasibility of the BP-NGD transient study is illustrated with experimentation based on ultra-wide band (UWB) pulse generator. As proof-of-concept, barcode NGD circuit exhibiting tri-band NGD value-center frequency-bandwidth, (−5.9 ns, 2.128 GHz, 20 MHz), (−7.4 ns, 2.3 GHz, 14 MHz) and (−4.8 ns, 2.42 GHz, 14 MHz) has been fabricated and tested. The transient simulations and experiences confirm that the output signal envelopes of the barcode NGD prototype present leading and tailing edges in time-advance of input ones when the carrier frequency is set equal to the NGD center frequency.

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Design of a reconfigurable compact digitally controlled oscillator (DCO is proposed in this paper. It uses a gyrator-C based-topology tunable active inductor (TAI) that achieves coarse frequency tuning due to a digitally controlled current source and a variable capacitance bank. The DCO, implemented in 130 nm CMOS process, achieves a frequency tuning from 1.8 to 2.6 GHz when varying the digital control word. It occupies an area of only $57\ \boldsymbol{\mu} \mathbf{m}\times 53\ \boldsymbol{\mu} \mathbf{m}$ . The power consumption is changing from 2.6 mW to 5.3 mW at a supply voltage of 1.1 V, and the phase noise from −86 to −82 dBc/Hz @1 MHz offset. The proposed DCO shows a compact size, wide tuning and low-power consumption making it suitable to reconfigurable low-cost multiband radiofrequency (RF) applications.

This paper presents a design of a CMOS digitally controlled oscillator (DCO) using a tunable active inductor (TAI) to reduce the area and cost for reconfigurable multi-band RF applications. The compatibility of this circuit to different wireless standards shows its potential to be implemented for the Internet of Things (IoT). The proposed TAI, based on a gyrator-C topology, achieves coarse frequency tuning due to a 4-bit digitally controlled current source. Implemented in 130 nm CMOS technology, the DCO occupies an area of only $(52\ \times 48)\ \mu\mathrm{m}^{2}$ . The circuit offers a frequency tuning from 1.65 GHz to 2.5 GHz for a 4-bit digital control word in [1], [15]. The optimal phase noise is about −87 dBc/Hz@1 MHz offset with power consumption varying from 2.6 mW to 5 mW at a supply voltage of 1.1 V when changing the control word digitally from 1 to 15.

In this study, a suitable sub-mW frequency down converter for internet of things is presented. It is based on a single balanced switched transconductance mixer driven by a current-reuse LC voltage controlled oscillator (LC-VCO). For cognitive radio demonstration, the frequency converter is implemented with a tunable low-noise amplifier (LNA) in 0.13 µm standard complementary metal oxide semiconductor (CMOS) technology. Post-layout simulations return a gain conversion of 27 dB with a single-sideband noise figure of 8 dB (LNA included) for a consumption of 0.97 mW under a voltage supply of 1.2 V and an active area of 0.4 mm2. The stand-alone LC-VCO prototype exhibits a measured phase noise of −102 dBc/Hz at 1 MHz offset while showing −114 dBc/Hz in the post-layout simulation. The LC-VCO measured power consumption is only 260 µW from 1 V voltage supply with an active area of 0.173 mm2.

International audience; A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

International audience

In this paper, an optimization technique for active inductor circuit forward noise, size area, and power dissipation is proposed through careful selection of the number of gate fingers N f of a nanoscale MOS transistor. According to simulation results, the application of supply voltage scaling and multi-gate finger transistor techniques can therefore introduce simultaneously a reduction in power consumption around 60% (from 3.35 to 1.32 mW) and a minimization in noise performance at 2 GHz from 3.15 to 2.1 ɳV/√Hz with a small size area and wide tuning range.

International audience; In this article, a design methodology of an active bandpass filter (BPF) using tun-able active inductor (TAI) achieving wide frequency contiguous tuning range (FTR) is presented. The tunable BPF is realized with a differential TAI (DTAI) employing two-reconfiguration mechanisms one for coarse-tuning using a control-lable current source while the fine-tuning is performed through a variable feedback resistance. The center frequency tuning is performed through the variation of the DTAI control voltages. A cross-coupled pair based negative resistance technique is also applied to compensate the resistive losses of equivalent RLC resonator. The filter performances are significantly improved using several optimization techniques such as voltage scaling and multigate finger techniques. The proposed BPF is simulated using 0.13 μm CMOS technology. The filter achieves an insertion loss (IL) of 26.62-33.45 dB over the tuning range 1.16-3.27 GHz with a relative band-width of 1.3%-3.4%. The noise figure and input 1-dB compression point at 1.84 GHz are 14.93 dB and 2.72 dBm, respectively. The designed RF filter consumes an average power of 5 mW at 1 V supply voltage.

International audience; Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm(2). The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of -116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is -107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 mu W from 0.6 V supply voltage, making it suitable for ultra low power applications.

This paper presents a sub-1mW radiofrequency voltage controlled oscillator (VCO) design optimization approach. The relation between components and specifications of the LC-VCO is studied, which allows to easily identify its design trade-offs. This approach has been applied to optimize the design of two different topologies of sub-1mW LC-VCOs in 130nm CMOS process suitable for IoT applications. The first VCO is using the current-reused technique and the second one is based on CMOS cross-coupled topology operating in the sub-threshold region. Post-layout simulation results in both circuits show a total power consumption of only $136\mu \mathrm {W}$ and $267\mu \mathrm {W}$ with a phase noise of-114dBc/Hz @lMHz at the operation frequency of 2.4GHz.

This brief presents a reconfigurable inductor-less voltage controlled oscillator (VCO) with low-power and low-cost performances making it suitable for IoT applications and applicable to the multi-standards. It uses an active inductor based on n-bits controlled CMOS inverters for coarse frequency tuning and diode varactor for fine frequency tuning. The example of a 3 bit digitally controlled oscillator has been implemented in a 0.13μm CMOS process. It can cover a frequency tuning of 1.28–2.6 GHz and thus can support the different standards of 2G, 3G, 4G and future 5G wireless systems. The fabricated LC-VCO occupies a small active area of only (54 × 59)μm2. The phase noise is −87 dBc/Hz @ 1MHz with a power consumption less than 4mW at a supply of 1.1V.

This paper provides a comprehensive review of reconfigurable active inductor circuit topologies. Three reported architectures with different reconfiguration techniques have been studied in order to properly select adequate solution for designing wide adjustable active inductor. The study of the different topologies is revealed from the point of view of simplicity of structure, frequency tuning and quality factor, and power consumption. A wide tuning range active inductor model implemented in 0.13 μm CMOS has been suggested and compared to other exiting topologies in terms of performances parameters.

In this paper, a reconfigurable active bandpass filter (BPF) has been designed and fabricated in a 130 nm CMOS technology to cover a wide tuning of radio-frequencies. The filter is based on active inductor comprising tow control voltages for inductance value, quality factor and central frequency tenability. Throughout the wide frequency range (1.82–4.44 GHz), the BPF achieves an average insertion loss of 9.27 ± 0.37 dB and a noise figure between 11.03 and 9.1 dB. Operating at supply voltage of 1 V, the circuit consumes 2.27–2.72 mW and occupies only 390×400 µm2 chip area.

International audience; Active inductors circuits are developed as an alternative solution for multiband systems. In this context, this paper presents a wide tunability, a low power, high-Q differential active inductor (DAI) using 0.13 mu m CMOS technology. This work proposes a DAI using two cascode-grounded active inductors and cross-coupled negative resistance to decrease the noise and to improve the quality factor. The inductance tuning range, quality factor, and other performance are improved by using a technique enabling to vary the current crossing the proposed circuit and by inserting a tunable feedback resistance. Results based on post-layout simulations (PLS) illustrate that the inductance tuning range from 79.8 to 495 nH resulting in a frequency tuning range from 3.19 to 0.784 GHz. An excellent tunable quality factor almost of 2600 is achieved at 1.47 GHz. The core DAI dissipates between 1.57 and 2.59 mW on a 1 V supply voltage. The circuit has an input 1 dB compression point Pin, 1 dB of -2.32 dBm. Simulated noise at 0.784 GHz is less than 3.48 nV/root Hz. The chip area of the DAI with testing pads is around 0.002 mm(2).

This paper presents the architecture of a digitally controlled oscillator (DCO) suitable for multi-standard radio frequency (RF) operation. The presented oscillator has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters control voltages. The oscillator can cover different frequency bands from 1.23 GHz to 2.46 GHz by varying digitally four inverters sequence. It consumes less than 4.4 mW under 1.1 V supply voltage. It occupies a chip area of (54 × 59) μm2 in 130 nm CMOS technology.

The charge-pump phase locked loop (CP-PLL) is a mixed signal system and it is a challenging task for a designer to analyze the exact switching behavior of the PLL using any general concept of feedback systems. As the order of the loop filter (LF) is enhanced to cancel pre-filter noise and spurious signals, the more complexity in analysis is inevitable. The PLL operating with a voltage switched charge-pump (VSCP) is a complicated system, since the system representation is not unique in all switching states of the phase and frequency detector (PFD). Therefore, it is not possible to characterize the system with a unique transfer function. In this paper, an exact discrete-time non-linear model of the VSCP-PLL is presented using efficient Event Driven (ED) modeling. By assuming a constant voltage at control node in the zero-state, the approximation model is demonstrated, which can be sufficient to use without complicating the analysis up to some extent. The ED-simulation of the exact model is validated using an equivalent transistor level model designed in 130nm CMOS process. The ability of both exact and approximation model is mapped applying a ramping reference frequency.

This paper presents a novel design and an optimization methodology of an ultra-low power and low phase noise RF voltage controlled oscillator (VCO). This VCO is based on a PMOS-NMOS cross-coupled topology operating in the subthreshold region. An adaptive body biasing technique is presented in this circuit leading to a high immunity to PVT (P=Process, V=Voltage, and T=Temperature) variations. The VCO, implemented in 130nm CMOS technology, consumes only 63 μW under 0.6 V. The obtained tuning range is about 7.2% from 2.32 GHz to 2.495 GHz; therefore, it can address many wireless communication standards such as Wi-Fi, ANT, ZigBee, IEEE 802.15.4, 6LoWPAN, and Bluetooth.

The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for 2nd and 3rd order PLL is achieved respectively.

This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different stages while the desired bandwidth is ensured due to an optimal sizing of the inter-stages connections. This approach has been validated with on chip measurements. Using the proposed techniques more than 55 dB of image rejection over the [1.5; 3.3] GHz bandwidth is demonstrated while achieving zero power consumption and small silicon area in 130nm CMOS technology.

Simple and low cost method based on Built-in-Tuning (BIT) of passive filters in RFIC transceiver is presented, which is used to compensate for variability induced imperfections in RF subsystems. Auto-calibration of filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio (IRR) and the I/Q-accuracy resulting to robust and low-cost solutions in multistandard wireless transceiver.

In this paper, a new tunable differential active inductor (DAI) architecture based on the use of two cascade-grounded active inductors is proposed. A negative resistance based cross-coupled pairs is added to improve the quality factor. The DAI has been implemented in 0.13μm CMOS process. The obtained simulation results show an inductance tuning range from 80 nH to 520 nH for circuit operating frequency range from 0.78 GHz to 3.25 GHz achieving 66% tuning range. A high quality factor of 2672 is obtained at the center frequency of 1.65 GHz. The power consumption is around 2.5 mW under 1V power supply. It occupies a small chip area of around 23.6 × 37.8 μm2.

A digitally controlled oscillator (DCO) suitable for multi-standards radio-frequency (RF) operation is presented. It has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters’ control voltages. The proposed DCO has a small area and exhibits a high-frequency tuning range while achieving low power consumption with good stability against process variations.

A compact reconfigurable CMOS low-noise amplifier (LNA) is presented for applications in DCS1800, UMTS, WLAN-b/g and Bluetooth standards. The proposed LNA features first a current reuse shunt-feedback amplifier for wideband input matching, low-noise figure and small area. Secondly, a cascode amplifier with a tunable active LC resonator is added for high gain and continuous tuning of bands. Fabricated in a 0.13 μm CMOS process, the measured results show >20 dB power gain

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The design and implementation of a CMOS integrated analog to digital interface dedicated to hybrid integration of MEMS resistive microphone is presented. Audio sensing is achieved with an innovative low-cost technology that uses single crystal piezoresistive silicon nanowires as transducer in a MEMS. The circuit composed of a low-noise instrumentation preamplifier followed by a single bit fourth order continuous-time sigma-delta modulator (CT-ΣΔM) includes bias circuit for sensor. To join low power applications where extensive digital processing is employed, 0.28 μm CMOS process with a 2.5 V supply has been adopted. The test chip occupies an area of 1 mm2. Post-layout simulation exhibits promising performances where noise density is below 8 nV/VHz within the frequency range from 10 Hz to 10 kHz. Complete interface circuit features a current consumption of 2.4 mA.

This paper presents a built-in tuning technique in radiofrequency receivers using on-chip polyphase filters. Auto-calibration of the filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio (IRR) and the I/Q-accuracy resulting in robust and low-cost solutions.

This paper presents a built-in tuning technique of local oscillator part of radiofrequency (RF) transceiver using onchip temperature sensor and process monitoring in order to cancel the process, voltage and temperature (PVT) drift of the modulating frequency. An auto-calibration of the VCO, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency of operation and results in low-cost, low power solutions.

This paper presents a reconfigurable inductor-less CMOS low noise amplifier (LNA) for multi-standard wireless applications. The LNA is designed to address PCS1900, UMTS, WLANb/g and Bluetooth frequency bands. The LNA is based on two cascaded stages. The first stage is a resistive feedback amplifier which achieves a wideband matching in order to address the different application frequency bands while performing a low noise figure. The second stage is a cascode amplifier with an active output LC resonator in order to select the desired bandwidth while achieving high gain and low surface area. The proposed multi-standard LNA, implemented in a 0.13µm CMOS technology achieves more than 26dB gain from 1.8 to 2.4GHz for a noise figure less than 3.4dB. The input and output return losses S11 and S22 are lower than −12dB and −16dB respectively. The LNA consumes 9.6 mA from 1.2V supply voltage and occupies a chip area of 0.165mm2 including pads.

A built-in tuning circuit of RadioFrequency (RF) Passive Polyphase Filter (PPF) for image rejection in low Intermediate Frequency (IF) receiver is presented. The resistance values of the filter are process dependent and can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low cost solution.

International audience

Design and implementation of an image-rejection double-quadrature radio frequency front-end receiver based on tunable polyphase filters (PPF) are presented in this article. The front-end consists of two sets of PPFs and a double-quadrature down-converter. The design contains devices that allow process spread and frequency drift control, making it suitable for multi-standard applications. Formal analysis and statistical method leading to the polyphase filter optimal sizing have been dealt with in this article. The effects of parasitic capacitances and component mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection ratio (IRR) performance. The front-end receiver exhibits more than 60 dB IRR and good linearity in high-frequency applications.

International audience; High performance RF front-end receiver suitable for telemeter solution for smartgrid is proposed in this article. It is based on a tunable polyphase filter topology to perform high image rejection. The design allows frequency control making it suitable for multi-standards applications. In order to improve the maximal achievable image rejection ratio (IRR), both formal analysis and statistical method leading to the filter optimal sizing have been dealt with. The effects of parasitic capacitances and components mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection performance. The proposed tunable polyphase filter has been used within a low-IF double-quadrature RF front-end receiver. More than 60dB IRR and good linearity in high frequency applications are ensured.

International audience

A 2.4GHz image rejection (IR) radio-frequency front-end receiver is proposed in this paper. It adopts double-quadrature architecture with polyphase filters to achieve high image rejection ratio (IRR). A tunable polyphase filter topology that allows counteracting the process spread and frequency drifts, making it suitable for multi-standards applications, is also dealt with. The IR front-end, implemented in 130nm standard CMOS technology, ensures more than 60dB IRR and good linearity in high frequency applications.

International audience

A tunable polyphase filter topology isproposed in this paper. The design is fitted with devicesthat allow counteracting the process spread andfrequency drifts making it suitable for multi-standardsapplications. In order to improve the maximalachievable image rejection ratio (IRR), both formalanalysis and statistical method leading to the filteroptimal sizing have been dealt with. The effects ofparasitic capacitances and components mismatch arealso considered and discussed. Steps within CMOSpolyphase filter design flow are then provided toguarantee high image rejection performance. Theproposed tunable polyphase filter has been used withina low-IF double-quadrature RF front-end receiver.More than 60dB IRR and good linearity in highfrequency applications are ensured.

Polyphase filters are an efficient solution for high image rejection and great accuracy quadrature generation in radio frequency (RF) receivers. Analytical modeling of passive polyphase filter suitable for RF front-end applications operating in 2.4 GHz frequency band is dealt with. This analytical analysis has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component matching techniques has been taken into account during the layout process. Tunable RC polyphase network has been fabricated in 0.13-µm CMOS technology.

A design of a 3.3 Volts BiCMOS buffer with current consumption and linearity control is presented. This buffer with a low output impedance is fully differential and designed to be used with RF (radio frequency) mixer in low IF (intermediate frequency) architecture. The proposed buffer is directly connected to the output of the RF mixer and designed to drive off- chip low impedance load as SAW (surface acoustic wave) or discrete differential filters. A good flexibility is obtained about the control of the linearity performance with the possibility to adjust the power consumption. The linearity and current consumption are independently adjustable and an optimum of the 3rd order linearity performance is achieved for each current consumption value. A schematic of the differential Bi-CMOS 3.3 volts buffer is proposed and some linearity simulation results are presented and discussed in terms of output IM3 level and current consumption. The results show a saving of half power in comparison with a buffer with no linearity control for the same output IM3 level.

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of -139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of-merit of -190 dBc/Hz is observed.

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. The QVCO could be tuned between 2.41 and 2.64 GHz, and showed a phase noise of-139 dBc/Hz at 1 MHz offset frequency from the carrier across the whole tuning range, for a current consumption of 20 mA with 2.5-V power supply. A figure-of- merit of-190 dBc/Hz is observed.