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Secret sharing is an important encryption technique in the field of information security. It can ensure the security of secret information. Textured 3D (three-dimensional) mesh model is an information carrier with a large amount of non-integer data. Therefore it takes longer time and computation to share them compared to 2D (two-dimensional) digital images. In this paper, different circuit modules are designed to accelerate the generation of shares and reconstruction of secrets. The hardware architecture enables security while sharing less data. In the data preprocessing phase, the correlation of the edge points of the texture vertices is utilized to filter the texture vertices, which reduces the amount of data to be shared. In the share generation phase, random factors are added. It makes the shares more secure and does not require group reconstruction. Simulation results show that the structure is more than 70 times faster compared to the software implementation. The optimized resource utilization is reduced by more than 60 % . The feasibility of the hardware architecture is verified by conducting experiments on several models and analyzing the results. [ABSTRACT FROM AUTHOR]

The next-generation "Industrial Internet of Things" (IIoT) will support "Machine-to-Machine" (M2M) communications for smart Cyber-Physical-Systems and Industry 4.0, and require guaranteed cyber-security. This paper explores hardware-enforced cyber-security for critical infrastructures. It examines a quantum-safe "Software-Defined-Deterministic IIoT" (SDD-IIoT), with a new forwarding-plane (sub-layer-3a) for deterministic M2M traffic flows. A "Software-Defined Networking" (SDN) control plane controls many "Software-Defined-Deterministic Wide-Area Networks" (SDD-WANs), realized with FPGAs. The SDN control plane provides an "Admission-Control/Access-Control" system for network-bandwidth, using collaborating Artificial Intelligence (AI)-based "Zero Trust Architectures" (ZTAs). Hardware-enforced access-control eliminates all congestion, BufferBloat, and DoS/DDoS attacks, significantly reduces buffer-sizes, and supports ultra-reliable-low-latency communications in the forwarding-plane. The forwarding-plane can: (i) Encrypt/Authenticate M2M flows using quantum-safe ciphers, to withstand attacks by Quantum Computers; (ii) Implement "guaranteed intrusion detection systems" in FPGAs, to detect cyber-attacks embedded within billions of IIoT packets; (iii) Provide guaranteed immunity to external cyber-attacks, and exceptionally strong immunity to internal cyber-attacks; (iv) Save USD 100s of billions annually by exploiting FPGAs; and (v) Enable hybrid Classical-Quantum networks, by integrating a "quantum key distribution" (QKD) network with a classical forwarding plane with exceptionally strong cyber-security, determined by the computational hardness of cracking Symmetric Key Cryptography. Extensive experimental results for an SDD-WAN over the European Union are reported. [ABSTRACT FROM AUTHOR]

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements. [ABSTRACT FROM AUTHOR]

Ensuring data security and integrity is crucial for achieving the highest level of protection and performance in modern cyber-physical systems (CPS). Authenticated encryption with associated data (AEAD) is an efficient and secure way to encrypt data that ensures confidentiality and authenticity. The proposed work focuses on image encryption using the TinyJAMBU cipher within the AEAD scheme. In this paper, image encryption using the TinyJAMBU cipher with software and hardware modeling has been proposed, and image encryption evaluation over standard matrices has been performed. The hardware architecture for TinyJAMBU has been implemented on the Xilinx Virtex-7 FPGA device. The implementation results are compared with the realization of other contemporary ciphers that make TinyJAMBU-128’s implementation better in terms of look-up tables (LUTs), slice utilization, and power consumption. In the experimentation phase, the results of TinyJAMBU-128/192/256 for image encryption have been compared with existing image encryption techniques. It has been observed that, compared to other implementations, the proposed image encryption application using TinyJAMBU provides better results for PSNR, MSE, RMSE, and UACI. [ABSTRACT FROM AUTHOR]

The leap forward in research progress in real-time object detection and classification has been dramatically boosted by including Embedded Artificial Intelligence (EAI) and Deep Learning (DL). Real-time object detection and classification with deep learning require many resources and computational power, which makes it more difficult to use deep learning methods on edge devices. This paper proposed a new, highly efficient Field Programmable Gate Array (FPGA) based real-time object detection and classification system using You Only Look Once (YOLO) v3 Tiny for edge computing. However, the proposed system has been instantiated with Advanced Driving Assistance Systems (ADAS) for evaluation. Traffic light detection and classification are crucial in ADAS to ensure drivers’ safety. The proposed system used a camera connected to the Kria KV260 FPGA development board to detect and classify the traffic light. Bosch Small Traffic Light Dataset (BSTLD) has been used to train the YOLO model, and Xilinx Vitis AI has been used to quantify and compile the YOLO model. The proposed system can detect and classify traffic light signals from a high-definition (HD) video streaming in 15 frames per second (FPS) with 99% accuracy. In addition, it consumes only 3.5W power, demonstrating the ability to work on edge devices. The on-road experimental results represent fast, precise, and reliable detection and classification of traffic lights in the proposed system. Overall, this paper demonstrates a low-cost and highly efficient FPGA-based system for real-time object detection and classification.

The ImageNet moment was a turning point for Convolutional Neural Networks (CNNs), as it demonstrated their potential to revolutionize computer vision tasks. This triumph of CNNs has motivated solving even more complex problems involving multiple tasks from multiple data modalities. Conventionally, a single CNN accelerator has been optimized to perform just one task or multiple correlated tasks. This study presents a shared-layers approach that leverages the pattern-learning capabilities of CNNs to perform multiple uncorrelated tasks from different modalities using a single hardware accelerator. We overcame the challenge of data imbalance in multi-modal learning by synthetic data generation. We achieved an average classification accuracy above 90% on a single CNN accelerator, which would otherwise require three accelerators. Due to the reliability concerns imposed by transistor shrinking and aging, we extended the shared layers methodology and introduced a fault-tolerant CNN accelerator with reconfigurable capabilities supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes. FT mode provides high reliability against soft errors utilizing double/triple modular redundancy, HP mode offers peak performance of 0.979 TOPs using parallel execution, and DS mode reduces dynamic power consumption by up to 68.6% in clock-gated design and even more using a partial reconfiguration method, contributing to decelerating the aging process of the circuit. We have comprehensively evaluated two different CNN architectures (i.e., fused and branched), for three distinct tasks, in three different operating modes, based on accuracy, quantization, pruning, hardware resource utilization, power, energy, performance, and reliability.

Field-programmable gate array (FPGA)-based real-time simulation plays a crucial role in testing power–electronic dominated systems with the formation of controller hardware-in-the-loop (CHIL) or power hardware-in-the-loop (PHIL). This work describes an efficient implementation of computation time and resource usage in the FPGA-based study of a modular multilevel converter (MMC) with detailed electromagnetic transients. The proposed modeling technique can be used in continuous control mode (CCM) and discontinuous control mode (DCM) for high-switching frequency semiconductor technologies. An FPGA-based designed solver structure is also presented to take advantage of the parallel features of FPGAs to achieve an ultra-fast calculation speed. In addition, two different switch modeling techniques are discussed with a five-level MMC case study. Experimental results on the NI PXIe platform show the feasibility of the proposed implementation, and a time step of 100 nanoseconds is achieved. [ABSTRACT FROM AUTHOR]

Modern embedded image processing deployment systems are heterogeneous combinations of general-purpose and specialized processors, custom ASIC accelerators and bespoke hardware accelerators. This paper offers a primer on hardware acceleration of image processing, focusing on embedded, real-time applications. We then survey the landscape of High Level Synthesis technologies that are amenable to the domain, as well as new-generation Hardware Description Languages, and present our ongoing work on IMP-lang, a language for early stage design of heterogeneous image processing systems. We show that hardware acceleration is not just a process of converting a piece of computation into an equivalent hardware system: that naive approach offers, in most cases, little benefit. Instead, acceleration must take into account how data is streamed throughout the system, and optimize that streaming accordingly. We show that the choice of tooling plays an important role in the results of acceleration. Different tools, in function of the underlying language paradigm, produce wildly different results across performance, size, and power consumption metrics. Finally, we show that bringing heterogeneous considerations to the language level offers significant advantages to early design estimation, allowing designers to partition their algorithms more efficiently, iterating towards a convergent design that can then be implemented across heterogeneous elements accordingly. [ABSTRACT FROM AUTHOR]

Approximate Computing Techniques (ACTs) take advantage of resilience computing applications to trade off among output precision, area, power, and performance. ACTs can lead to significant gains at affordable costs when efficiently implemented on Field Programmable Gate Array– (FPGA) based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems: Does ACT optimization negatively affect the reliability of the system and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimization Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming alternative to the MOP if a complete Pareto-front is not needed. Our methodology generates fault-tolerant versions of the Pareto-optimal approximate designs (or simple optimized approximate designs if the ScOP choice is picked) by selectively applying mitigation techniques in a way that the overheads of redundant resources for fault-tolerance do not negate the gains of approximation in comparison to the fault-tolerant versions of the precise design. We evaluate our method on two FPGA-based accelerators: a JPEG encoder and an H.264/Advanced Video Coding decoder. Our experimental results show significant gains in area, frequency, and power consumption without compromising output quality and system reliability compared to classic solutions that replicate all or a part of the resources of the precise design to increase dependability metrics. [ABSTRACT FROM AUTHOR]

A Fuzzy Inference System (FIS) is a system that represents human reasoning based on fuzzy if-then rules to extract valid results from imprecise or uncertain information. These systems have been applied to various engineering fields, such as control and image recognition, and have encouraged the search for development tools that provide facilities for the design, simulation, and implementation of FISs. Most of the available software tools for the design of FISs have been developed by the scientific community, and very few are commercial tools. According to the state of the technology, the fuzzy systems implemented in hardware have shown higher performance than software implementations. For this reason, different strategies for automatic hardware synthesis of FISs have been proposed in the literature. The available tools for FIS implementation, including MATLAB, Simulink, and Xfuzzy environment, require advanced hardware knowledge, and it is necessary to synthesize and implement the program on FPGA each time a change is made to the code. This paper presents a novel approach for the implementation of fuzzy systems on hardware devices that enables the direct implementation of FISs through a graphical user interface. The VHDL code is pre-synthesized and integrated with the interface, allowing users to experiment with different input parameters, such as membership functions and fuzzy rules, without resynthesizing the code on an FPGA. To verify the effectiveness of the proposed approach, experiments were conducted on two similar System-on-Chip (SoC) devices, VEEK-MT and VEEK-MT2. The results showed that the proposed solution represents a significant advancement in the study of fuzzy systems on hardware devices, providing a flexible and user-friendly approach to their design and implementation. [ABSTRACT FROM AUTHOR]

In the era of climate change, and with the rapid depletion of fossil resources, efficient and sustainable transportation systems, such as hybrid electric vehicles (HEVs), are becoming imperative. The cornerstone of HEVs is the efficient battery technology, in order to extend the useful life of the battery and to provide improved performance to fossil fuel technology. Model predictive control (MPC) is an effective technique for battery management systems (BMS), which enables cell-level monitoring and controlling of the battery pack, reducing the safety margin of operation, while maintaining the safety requirements. Furthermore, utilizing the physics-based model (PBM) of the battery allows the control system to operate on the chemical and physical process of the battery that are the root cause of battery degradation. The non-linear extended Kalman filter (EKF) serves as the state observer to monitor the physical and chemical properties/processes of each battery cell, since these are internal processes of the battery, making them physically unobservable. The amalgamation of the aforementioned techniques, i.e., MPC, PBM, and EKF, can extend the useful life of the battery cell/pack, especially for lithium-ion batteries. In real-world scenarios, HEVs and smart applications often require portable BMS, compelling BMS to be executed on highly constrained embedded devices. Also, the inherent adaptive control process of physics-based (PB) MPC is uniquely suited for smart systems/applications. However, the high computational complexity of PB-MPC, comprising PB-EKF, prevents it from being realized on resource-constrained embedded devices, making it infeasible for portable BMS. In this research work, we introduce novel, unique, and efficient FPGA-based embedded hardware accelerator for PB-MPC smart sensor (comprising PB-EKF) for BMS, specifically on embedded devices, by addressing the computational complexity of PBM. Our proposed embedded PB-MPC hardware accelerator achieved 58 times speedup compared to its embedded software counterpart, while maintain a small footprint required for portable systems. This speedup enables us to manage more battery cells utilizing a single chip compared to that of embedded processor-based solutions.

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs. [ABSTRACT FROM AUTHOR]

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

Field-programmable gate array (FPGA)-based real-time simulation plays a crucial role in testing power–electronic dominated systems with the formation of controller hardware-in-the-loop (CHIL) or power hardware-in-the-loop (PHIL). This work describes an efficient implementation of computation time and resource usage in the FPGA-based study of a modular multilevel converter (MMC) with detailed electromagnetic transients. The proposed modeling technique can be used in continuous control mode (CCM) and discontinuous control mode (DCM) for high-switching frequency semiconductor technologies. An FPGA-based designed solver structure is also presented to take advantage of the parallel features of FPGAs to achieve an ultra-fast calculation speed. In addition, two different switch modeling techniques are discussed with a five-level MMC case study. Experimental results on the NI PXIe platform show the feasibility of the proposed implementation, and a time step of 100 nanoseconds is achieved.

We examine how to provide applications with dedicated bandwidth and guaranteed latency in a programmable mission-critical network. Unlike other SDN approaches such as B4 or SWAN, our system Tuneman optimizes both routes and packet schedules at each node to provide flows with sub-second bandwidth changes. Tuneman uses node-level optimization to compute node schedules in a slotted switch and does dynamic routing using a search procedure with Quality of Service– (QoS) based weights. This allows Tuneman to provide an efficient solution for mission-critical networks that have stringent QoS requirements. We evaluate Tuneman on a telesurgery network using a switch prototype built using FPGAs and also via simulations on India’s Tata Network. For mission-critical networks with multiple QoS levels, Tuneman has comparable or better utilization than SWAN while providing delay bounds guarantees. [ABSTRACT FROM AUTHOR]

Image registration is a well-defined computation paradigm widely applied to align one or more images to a target image. This paradigm, which builds upon three main components, is particularly compute-intensive and represents many image processing pipelines’ bottlenecks. State-of-the-art solutions leverage hardware acceleration to speed up image registration, but they are usually limited to implementing a single component. We present Faber, an open-source HW/SW CAD toolchain tailored to image registration. The Faber toolchain comprises HW/SW highly-tunable registration components, supports users with different expertise in building custom pipelines, and automates the design process. In this direction, Faber provides both default settings for entry-level users and latency and resource models to guide HW experts in customizing the different components. Finally, Faber achieves from 1.5× to 54× in speedup and from 2× to 177× in energy efficiency against state-of-the-art tools on a Xeon Gold. [ABSTRACT FROM AUTHOR]

Deep neural networks (DNNs) have played an increasingly important role in various areas such as computer vision and voice recognition. While training and validation become gradually feasible with high-end general-purpose processors such as graphical processor units (GPU), high throughput inferences in embedded hardware platforms with low hardware resources and power consumption efficiency are still challenging. Binarized neural networks (BNNs) are emerging as a promising method to overcome these challenges by reducing bit widths of DNN data representations with many optimal prior solutions. However, accuracy degradation is a considerable problem of the BNN, compared to the same architecture with full precision, while the binary neural networks still contain significant redundancy for optimization. In this paper, to address the limitations, we implement a streaming accelerator architecture with three optimization techniques: pipelining-unrolling for streaming each layer, weight reuse for parallel computation, and MAC (multiplication-accumulation) compression. Our method first constructs streaming architecture by pipelining-unrolling method to maximize throughput. Next, the weight reuse method with the K-mean cluster is applied to reduce the complexity of the popcount operation. Finally, MAC compression reduces hardware resources used for remaining computation on MAC operations. The implemented hardware accelerator integrated into a state-of-the-art field programable gate array (FPGA) provides the maximum performance of the classification at 1531k frames per second with 98.4% accuracy for the MNIST dataset and 205K frame per second with 80.2% accuracy for the Cifar-10 dataset. Besides, the proposed design’s ratio FPS/LUTs is approximately 57 (MNIST) and 0.707 (Cifar-10), which is much lower than the state-of-the-art design with a comparable throughput and inference accuracy.

We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 $\mu \text{s}$ , enabling radio applications in which latency is a principal constraint.

In medical and health sciences, the detection of cell injury plays an important role in diagnosis, personal treatment and disease prevention. Despite recent advancements in tools and methods for image classification, it is challenging to classify cell images with higher precision and accuracy. Cell classification based on computer vision offers significant benefits in biomedicine and healthcare. There have been studies reported where cell classification techniques have been complemented by Artificial Intelligence-based classifiers such as Convolutional Neural Networks. These classifiers suffer from the drawback of the scale of computational resources required for training and hence do not offer real-time classification capabilities for an embedded system platform. Field Programmable Gate Arrays (FPGAs) offer the flexibility of hardware reconfiguration and have emerged as a viable platform for algorithm acceleration. Given that the logic resources and on-chip memory available on a single device are still limited, hardware/software co-design is proposed where image pre-processing and network training were performed in software, and trained architectures were mapped onto an FPGA device (Nexys4DDR) for real-time cell classification. This paper demonstrates that the embedded hardware-based cell classifier performs with almost 100% accuracy in detecting different types of damaged kidney cells. [ABSTRACT FROM AUTHOR]

With the technological improvement in artificial intelligence, particularly deep learning is providing effective outcomes along with hardware platforms such as field-programmable gate arrays (FPGAs) and graphics processing units in various domains. FPGAs with their reconfigurable architectures provide flexibility, better performance and high levels of parallelism. Object detection is one of the prominent areas of research in the fields of computer vision and image processing applications. You Only Look Once (YOLO) is a state-of-the art object detection algorithm which is fast and accurate. However, many applications require accuracy and rapid processing for better results. For such conditions, these algorithms can be implemented on hardware accelerators. This work proposes the implementation of YOLOv4 algorithm on Xilinx® Zynq-7000 System on a chip and is suitable for real-time object detection. The proposed work shows better resource utilization of about 23.2 k (43.6%) of Look-up tables, 45.8 k (43.04%) of Flip-flops, 115 (82.17%) BRAMs and 174 (79%) DSPs achieving at 100 MHz frequency which is more efficient on comparing with other simulation results. [ABSTRACT FROM AUTHOR]

Today's intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the frequent loss of computational state. To remedy this problem, intermittent computing systems comprise built-in fast non-volatile memories with high write endurance to store information that persists despite frequent power failures. However, the lack of design tools makes fast-prototyping these systems difficult. Even though FPGAs are common platforms for fast prototyping and behavioral verification of continuously powered architectures, they do not target prototyping intermittent computing systems. This article introduces a new FPGA-based framework, named NORM (Non-volatile memORy eMulator), to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories. Our evaluation showed that NORM can be used to emulate and validate FeRAM-based transiently powered hardware architectures successfully. [ABSTRACT FROM AUTHOR]

Entropy is one of the most fundamental notions for understanding complexity. Among all the methods to calculate the entropy, sample entropy (SampEn) is a practical and common method to estimate time-series complexity. Unfortunately, SampEn is a time-consuming method growing in quadratic times with the number of elements, which makes this method unviable when processing large data series. In this work, we evaluate hardware SampEn architectures to offload computation weight, using improved SampEn algorithms and exploiting reconfigurable technologies, such as field-programmable gate arrays (FPGAs), a reconfigurable technology well-known for its high performance and power efficiency. In addition to the fundamental disclosed straightforward SampEn (SF) calculation method, this study evaluates optimized strategies, such as bucket-assist (BA) SampEn and lightweight SampEn based on BubbleSort (BS-LW) and MergeSort (MS-LW) on an embedded CPU, a high-performance CPU and on an FPGA using simulated data and real-world electrocardiograms (ECG) as input data. Irregular storage space and memory access of enhanced algorithms is also studied and estimated in this work. These fast SampEn algorithms are evaluated and profiled using metrics such as execution time, resource use, power and energy consumption based on input data length. Finally, although the implementation of fast SampEn is not significantly faster than versions running on a high-performance CPU, FPGA implementations consume one or two orders of magnitude less energy than a high-performance CPU. [ABSTRACT FROM AUTHOR]

Object detection is one of the most challenging tasks in computer vision. With the advances in semiconductor devices and chip technology, hardware accelerators have been widely used. Field-programmable gate arrays (FPGAs) are a highly flexible hardware platform that allows customized reconfiguration of the integrated circuit, which has the potential to improve the efficiency of object detection accelerators. However, few reviews summarize FPGA-based object detection accelerators. Also, there is no general principle for realizing object detection according to FPGA characteristics. In this paper, the current hardware accelerators are introduced and compared. Then, the typical deep learning-based object detectors are summarized. Next, the questions of "Why choose FPGA," "The design goals of FPGA accelerators" and "The design methods for FPGA accelerators" are discussed in detail. Finally, the challenges of object detection algorithms, hardware, and co-design are presented. In addition, an online platform (https://github.com/vivian13maker/) is constructed to provide specific information on all advanced works. [ABSTRACT FROM AUTHOR]

Convolution features huge complexity and demands high computation capability. Among hardware platforms, field programmable gate array (FPGA) emerges as a promising solution for its substantial available parallelism and energy efficiency. Besides, convolution can be implemented with different algorithms, including conventional, general matrix–matrix multiplication (GEMM), Winograd, and fast Fourier transformation (FFT) algorithms, which are diverse in arithmetic complexity, resource requirement, etc. Different convolutional neural network (CNN) models have different topologies and structures, favoring different convolution algorithms. In response, software libraries such as cuDNN provide a variety of computational primitives to support these algorithms. However, supporting such libraries on FPGAs is challenging. First, multiple algorithms can share the FPGA resources spatially as well as temporally, introducing either reconfiguration overhead or resource underutilization. Second, FPGA implementation remains a significant challenge for library developers. It typically requires significant specialized hardware knowledge. In this article, we propose FCNNLib, an efficient and scalable convolution algorithm library on FPGAs. To coordinate multiple convolution algorithms on FPGAs, we develop three schedulings: 1) spatial; 2) temporal; and 3) hybrid, which exhibit different tradeoffs in latency and throughput. We explore these schedulings by balancing the reconfiguration overhead, resource utilization, and optimization objectives of the CNNs. Then, we provide efficient and tunable algorithm templates that allow performance tuning through performance and resource models. To arm the users, FCNNLib exposes a set of interfaces to support high-level application designs. We demonstrate the usability of FCNNLib with state-of-the-art CNNs. FCNNLib achieves up to $44.6\times $ and $1.76\times $ energy efficiency in various scenarios compared with software libraries for CPUs and GPUs, respectively. [ABSTRACT FROM AUTHOR]

Object tracking and motion detection are the major challenges in the real-time image and video processing applications. There are several tracking and prediction algorithms available to estimate and predict the state of a system. Kalman filter is the most widely used prediction algorithm as it is very simple, efficient and easy to implement for linear measurements. However, these types of filter algorithms are customized on hardware platforms such as Field-Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs) to achieve design requirements for embedded applications. In this work, a multi-dimensional Kalman filter (MDKF) algorithm is proposed for object tracking and motion detection. The numerical analysis of proposed tracking algorithm achieves competitive tracking performance in contrast with state-of-the-art tracking algorithms trained on standard benchmarks. Furthermore, MDKF is implemented on Xilinx Zynq™-7000 System-on-a chip (SoC). The implementation of MDKF on SoC performs 2× times tracking speed than that of software approach. The experimental results provide resource utilization of about 61.43% of Block RAMs (BRAMs), 90.09% of DSPs, 83.27% of Look-up tables (LUTs) and 82.35% of logic cells operating at 140 MHz with power consumption of 780 mW which outperforms previous related methods.

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs.

Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The inference process of a Deep Neural Network (DNN) is considered a computationally intensive process that requires hardware accelerators to operate in real-world scenarios due to the low latency requirements of real-time applications. As a result, High-Level Synthesis (HLS) tools are gaining popularity since they provide attractive ways to reduce design time complexity directly in register transfer level (RTL). In this paper, we implement a MobileNetV2 model using a state-of-the-art HLS tool in order to conduct a design space exploration and to provide insights on complex hardware designs which are tailored for DNN inference. Our goal is to combine design methodologies with sparsification techniques to produce hardware accelerators that achieve comparable error metrics within the same order of magnitude with the corresponding state-of-the-art systems while also significantly reducing the inference latency and resource utilization. Toward this end, we apply sparse matrix techniques on a MobileNetV2 model for efficient data representation, and we evaluate our designs in two different weight pruning approaches. Experimental results are evaluated with respect to the CIFAR-10 data set using several different design methodologies in order to fully explore their effects on the performance of the model under examination. [ABSTRACT FROM AUTHOR]

With the increasing demand for convolutional neural networks (CNNs) in many edge computing scenarios and resource-limited settings, researchers have made efforts to apply lightweight neural networks on hardware platforms. While binarized neural networks (BNNs) perform excellently in such tasks, many implementations still face challenges such as an imbalance between accuracy and computational complexity, as well as the requirement for low power and storage consumption. This paper first proposes a novel binary convolution structure based on the time domain to reduce resource and power consumption for the convolution process. Furthermore, through the joint design of binary convolution, batch normalization, and activation function in the time domain, we propose a full-BNN model and hardware architecture (Model I), which keeps the values of all intermediate results as binary (1 bit) to reduce storage requirements by 75%. At the same time, we propose a mixed-precision BNN structure (model II) based on the sensitivity of different layers of the network to the calculation accuracy; that is, the layer sensitive to the classification result uses fixed-point data, and the other layers use binary data in the time domain. This can achieve a balance between accuracy and computing resources. Lastly, we take the MNIST dataset as an example to test the above two models on the field-programmable gate array (FPGA) platform. The results show that the two models can be used as neural network acceleration units with low storage requirements and low power consumption for classification tasks under the condition that the accuracy decline is small. The joint design method in the time domain may further inspire other computing architectures. In addition, the design of Model II has certain reference significance for the design of more complex classification tasks. [ABSTRACT FROM AUTHOR]

As one of the key technologies in spacecraft data-handling networks mounting high-resolution payloads, the multi-lane native SpaceFibre standard is designed to meet the demands for the high-speed and reliable interconnections between satellite payloads. A few studies are about the implementations of a multi-lane SpaceFibre core. Even though they exhibit good performance, several limitations still, more or less, exist. We detail an efficient multi-lane SpaceFibre (E-ML-SpFi) core for high-rate and fault-tolerant data communication. The E-ML-SpFi core exploits a hierarchical method to decouple the complex control logic of the retransmission mechanism. The core employs a modified word re-ordering block to map an extended set of words on a real-time variable number of data-sending lanes. Meanwhile, the core introduces the architecture of a fast alignment subsystem to accelerate the alignment process. A hardware implementation on XC7Z100 FPGA shows that the E-ML-SpFi core has complete functionality stipulated by the standard and requires limited resources, with 6290 (2.26%) LUTs and 8252 (1.49%) FFs. The maximum operating frequency of the core is 200 MHz. Moreover, the recovery time is reduced up to 30.9% compared with previous work. Therefore, the core provides a valid solution for future interconnection networks onboard spacecraft. [ABSTRACT FROM AUTHOR]

Physical unclonable functions (PUFs) are known as one of the most recent promising technologies for cryptographic key generation. A PUF circuit is designed in such a way to produce random digits based on true-random and uncontrollable variations during the integrated circuits (IC) manufacturing process. The response of PUF can be used as a unique identity for the device where the PUF is embedded in it. Field-programmable gate arrays (FPGAs) are usually considered as one of the first choices for implementing PUFs. This paper proposes a novel FPGA-derived Anderson PUF by optimizing all elements located in one configurable logic blocks (CLBs). The experimental results on Spartan-6 family Xilinx XC6SLX9 FPGAs show that the proposed architecture improves the PUF's uniformity, uniqueness, and reliability to 49.41%, 50.89%, and 91.25%, respectively. Furthermore, the proposed structure increases the complexity and unpredictability of the PUF while decreases the hardware area overhead.

Matrix computing is a basic operational model that was broadly used in science and engineering applications. In this study, we first propose a novel optimization method to obtain a high-performance and scalable architecture for matrix multiplication, including reducing data transmission, optimizing data flow, improving resource utilization, and dynamically changing the length of the linear array. Based on the optimized architecture, we present a multi-operation floating-point matrix computing unit (design-I), which extends the function of matrix computing from single matrix multiplication operation to matrix addition, matrix subtraction, matrix-vector multiplication, matrix-scalar multiplication. With low storage demand and computing efficiency, design-I can be used in computing dense matrices of arbitrary sizes. Moreover, we propose a continuous floating-point matrix computing unit (design-II), which not only has the same function of multi-operation but also meets the requirement of continuous matrix computing in practical engineering and avoids a large amount of intermediate data transfer. Finally, the authors adopt the above-mentioned unit cores to build a matrix computing acceleration system according to different engineering requirements. The experiments implemented in the Xilinx 585T FPGA device show that the accelerator achieves a maximum frequency of 195Mhz with 256 processing elements (PEs) and performs 99.8GFLOPS. The architecture is more outstanding in application scope and prospects compared with state-of-the-art methods.

With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multi-ported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bi-directional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bi-directional multi-ported memory designs. These results and analyses illustrate that our bi-directional multi-ported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost.

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA's many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device's security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem, especially in the high interaction density conditions expected during the future high-luminosity phase of the LHC (HL-LHC). Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task by embedding tracker data as a graph—nodes represent hits, while edges represent possible track segments—and classifying the edges as true or fake track segments. However, their study in hardware- or software-based trigger applications has been limited due to their large computational cost. In this paper, we introduce an automated translation workflow, integrated into a broader tool called hls4ml, for converting GNNs into firmware for field-programmable gate arrays (FPGAs). We use this translation tool to implement GNNs for charged particle tracking, trained using the TrackML challenge dataset, on FPGAs with designs targeting different graph sizes, task complexites, and latency/throughput requirements. This work could enable the inclusion of charged particle tracking GNNs at the trigger level for HL-LHC experiments.

Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, indexing databases, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. In this paper, the hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq®-7000 System on-Chip (SoC) device. It consists of Dual-core Cortex™-A9 processors which provide computing ability to perform I/O and processing functions and software libraries using Vivado® High-Level Synthesis (HLS). In the proposed work, Sobel-Feldman filter, posterize and threshold filter algorithms are implemented for 1920 x 1080 image resolutions. The implementation results exhibit effective resource utilization such as 45.6% of logic cells, 51% of Look-up tables (LUTs), 29.47% of Flip-flops, 15% of Block RAMs and 23.63% of DSP slices under 100 MHz frequency on comparing with previous works. [ABSTRACT FROM AUTHOR]

Infrared and visible image fusion is a beneficial processing task for Unmanned Aerial Vehicle (UAV) surveillance, which can improve visibility by combining the advantages of the infrared camera and the visible light camera. An embedded onboard solution is necessary for UAV-based surveillance missions because it reduces the amount of data that are transmitted to the ground. In this paper, we propose an infrared and visible light image fusion method and implement it on two platforms with commonly used HW accelerators for embedded vision applications: Zedboard (ARM + FPGA) and NVIDIA TX1 (ARM + GPU), and compare their performances. To verify the usefulness of image fusion, we carry out sufficient experiments to prove that image fusion can improve the target detection ability of a UAV in different scenes. The detection rate for target detection is up to 0.926 in our experiments. The execution times on the ZedBoard and the TX1 are, respectively, 205.3 FPS and 36.6 FPS (38 × and 6.7 × in comparison to an ARM Cortex-A9 processor). Our results also show that the ZedBoard achieves an energy/frame reduction ratio of 7.1 × and 18.9 × respectively compared to the TX1 and the ARM CPU. This work is based on a UAV platform designed by ourselves, and all image sets are real scenes that we have captured. This demonstrates that the proposed method is viable and reflects the actual needs of real UAV surveillance systems. [ABSTRACT FROM AUTHOR]

The achievement of the time-step below 500-ns in the field-programmable-gate-arrays (FPGAs)-based real-time simulation is of importance for the power converters having high switching frequencies. However, most of the existing focus on addressing the power converter modeling under the continuous conduction mode (CCM). Nevertheless, toward practical applications, the modeling of discontinuous conduction mode (DCM) with a light-load is of a greater challenge due to the “chattering” around zero point. In order to solve the chattering problem under the light-load, this article proposes a zero-regulation (ZR) method for FPGA-based real-time simulation. The proposed ZR method can not only represent CCM and DCM with a unified formula but also solve the chattering problem and improve accuracy and stability. In addition, results using different switch models are also given to demonstrate the feasibility and the generality of the proposed method. Finally, a case study of the series load resonant converter is presented. Simulation results are validated against a reference model at a 100-ns time step and a 10-kHz switching frequency. [ABSTRACT FROM AUTHOR]

This paper presents attacks targeting the FPGAs of AWS F1 instances at the electrical level through power-hammering, where excessive dynamic power is used to crash FPGA instances. We demonstrate different power-hammering attacks that pass all AWS security fences implemented on F1 instances, including the FPGA vendor design rule checks. In addition, we fingerprint the FPGA instances to observe the responsiveness of the instances, which indicates a successful denial-of-service attack. Most importantly, we provide an FPGA virus scanner framework, which was improved to support large datacenter FPGAs for preventing such attacks, including virtually all currently demonstrated side-channel attacks. Our experiments showed that an AWS F1 instance crashes immediately by starting an FPGA design demanding 369W. By using FPGA-fingerprinting, we found that crashed instances are unavailable for about one to over 200 hours.

Moving object tracking is a computation-intensive operation that requires accelerating hardware solution. In this work, a high-performance design for mean shift based moving object tracking algorithm and its FPGA implementation is done. Here, associated circuits are utilized as intellectual-property cores to implement an embedded system-on-a-chip (SoC) framework for real-time moving object tracking application. Real-time video with 640 × 480 resolution at 60 frames per second is captured and buffered in SDRAM, and processing is performed on the temporal frames. In the implemented FPGA-SoC framework, PowerPC processor embedded inside the FPGA device is used for the platform configuration, IPs control, and running the application program. The design require 30.08% slices, 35.14% BRAMs, and 43.75% DSP48E slices of Xilinx Virtex-5 xc5vfx70t FPGA device on the ML-507 platform. The computed power is 48.3 mW. [ABSTRACT FROM AUTHOR]

J-PARC E16 is an experiment to examine the origin of hadron mass through a systematic measurement of spectral changes of vector mesons in nuclei. The measurement of $e^{+}e^{-}$ pairs from the decay of vector mesons will provide the information of the partial restoration of the chiral symmetry in a normal nuclear density. To resolve a pulse pile-up and achieve good discrimination of $e^{+}$ and $e^{-}$ from the background of a reaction rate of an order of 10 MHz, the data acquisition (DAQ) system uses waveform sampling chips of APV25 and DRS4. The trigger rate and data rate are expected to be 1 kHz and 120–330 MiB/s, respectively. The DAQ system for readout of APV25 and DRS4 were developed, where events were synchronized by common trigger and tag data. The first commissioning in beam, called Run-0a, was performed in June 2020 with about 1/4 of the designed setup. The DAQ worked with a trigger rate of 300 Hz in the Run-0a and the main bottleneck was a large data size of APV25. Further optimization of the DAQ system will improve the performance. [ABSTRACT FROM AUTHOR]

In this article, we investigate the performance bottleneck of existing deep learning (DL) systems and propose DLBooster to improve the running efficiency of deploying DL applications on GPU clusters. At its core, DLBooster leverages two-level optimizations to boost the end-to-end DL workflow. On the one hand, DLBooster selectively offloads some key decoding workloads to FPGAs to provide high-performance online data preprocessing services to the computing engine. On the other hand, DLBooster reorganizes the computational workloads of training neural networks with the backpropagation algorithm and schedules them according to their dependencies to improve the utilization of GPUs at runtime. Based on our experiments, we demonstrate that compared with baselines, DLBooster can improve the image processing throughput by 1.4× – 2.5× and reduce the processing latency by 1/3 in several real-world DL applications and datasets. Moreover, DLBooster consumes less than 1 CPU core to manage FPGA devices at runtime, which is at least 90 percent less than the baselines in some cases. DLBooster shows its potential to accelerate DL workflows in the cloud. [ABSTRACT FROM AUTHOR]

This paper presents a simple but effective strategy to implement signed binary multipliers on Field Programmable Gate Arrays (FPGAs). It is based on the radix-4 Booth's encoding logic but adopts an unconventional sequence of logic operations that allows hardware resources to be more efficiently exploited. The main idea consists in preliminarily generating incorrect partial products, which allows the encoding logic to be simplified, and then correcting them in the subsequent computational steps, without requiring additional logic resources. The adopted approach uses both the look up tables (LUTs) and the fast carry-chains (CCs) available within FPGA devices. When implemented on a Xilinx xc7v585ttfg1157–3 device, a 32 × 32 multiplier designed as proposed here achieves a maximum running frequency of ∼217 MHz consuming only ∼216pJ per operation and using 792 LUTs and 147 CCs. When adopted in the realization of a 3 × 3 Multiply-Accumulate unit, in comparison with the lowest energy consuming competitor, the proposed approach leads to an energy-delay product 5.2 % lower and allows reducing the number of utilized LUTs and carry-chains by 25.2 % and 41.4 %, respectively. [ABSTRACT FROM AUTHOR]

Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-the-art hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget).

A novel platform for launching and using field-programmable gate arrays (FPFA) custom computing machines (CCMs) in clouds and data centers is proposed. Based on a developed FPGA virtualization scheme, it allows users to create independent computing services on network-attached standalone FPGAs. The interface of the virtual FPGA (vFPGA)-based CCM is automatically generated by a virtualization layer and based on the user's specifications. An FPGA hypervisor has been developed that can be easily integrated with any cloud management tool. It allows the users to launch/use/tear down vFPGA-based CCMs in a similar manner to conventional virtual machines (VMs). A complete prototype of the proposed platform has been realized and tested with a streamed image processing application. Its performance was 3-4x and ~1.4-2.4x times better than an SW implementation on a VM and a powerful server, respectively. Compared with other platforms for FPGA attachment to a cloud or datacenter, the proposed platform has relatively low overhead in terms of FPGA resources while providing the highest level of abstraction and virtualization.