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Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1. [ABSTRACT FROM AUTHOR]

In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the "real fail" state or "fake fail" state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design. [ABSTRACT FROM AUTHOR]

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation scheme for machine learning applications. When applied to a modified ResNet18 network trained under the CIFAR-10 dataset, the simulations indicate that the proposed CCLUTM-based DNV-CIM can achieve a peak energy efficiency of 75.18 TOPS/W with 4-bit multiplication and accumulation (MAC) operations. [ABSTRACT FROM AUTHOR]

This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation. [ABSTRACT FROM AUTHOR]

Artificial neural networks have acquired remarkable achievements in the field of artificial intelligence. However, it suffers from catastrophic forgetting when dealing with continual learning problems, i.e., the loss of previously learned knowledge upon learning new information. Although several continual learning algorithms have been proposed, it remains a challenge to implement these algorithms efficiently on conventional digital systems due to the physical separation between memory and processing units. Herein, a software–hardware codesigned in‐memory computing paradigm is proposed, where a mixed‐precision continual learning (MPCL) model is deployed on a hybrid analogue–digital hardware system equipped with resistance random access memory chip. Software‐wise, the MPCL effectively alleviates catastrophic forgetting and circumvents the requirement for high‐precision weights. Hardware‐wise, the hybrid analogue–digital system takes advantage of the colocation of memory and processing units, greatly improving energy efficiency. By combining the MPCL with an in situ fine‐tuning method, high classification accuracies of 94.9% and 95.3% (software baseline 97.0% and 97.7%) on the 5‐split‐MNIST and 5‐split‐FashionMNIST are achieved, respectively. The proposed system reduces ≈200 times energy consumption of the multiply‐and‐accumulation operations during the inference phase compared to the conventional digital systems. This work paves the way for future autonomous systems at the edge. [ABSTRACT FROM AUTHOR]

The Echo State Networks (ESNs) is a class of recurrent neural network (RNN), which can significantly reduce the training complexity since the input layer and middle layer (reservoir) are random fixed networks. In this letter, we propose a hardware-software co-design platform to implement memristor crossbar arrays for ESN model. We propose the programming with delayed pulse (PDP) scheme to improve the network performance by suppressing the degradation of the memristor. We optimized the spectral radius (SR) of the ESNs model. In addition, the programming scheme can also effectively improve the timing prediction capability of the memristor-based ESN network. When the prediction length is set to 1000, the Normalized Root Mean Square Error (NRMSE) of the ESN can be optimized by 56 times. [ABSTRACT FROM AUTHOR]

We investigated the thermal stability of a 1Mbit OxRRAM array embedded in 28 nm COMS technology. A back-end-of-line (BEOL) solution with a TaN–Ta interfacial layer was proposed to eliminate the failure rate after reflow soldering assembly at 260 °C. By utilizing a TaN–Ta interfacial layer (IL), the oxygen defects in conductive filament were redistributed, and electromigration lifetimes of Cu-based damascene interconnects were improved, which contributed to optimization. This work provides a potential solution for the practical application of embedded RRAM beyond the 28 nm technology node. [ABSTRACT FROM AUTHOR]

The growing demand for scalable solar‐blind image sensors with remarkable photosensitive properties has stimulated the research on more advanced solar‐blind photodetector (SBPD) arrays. In this work, the authors demonstrate ultrahigh‐performance metal‐semiconductor‐metal (MSM) SBPDs based on amorphous (a‐) Ga2O3 via a post‐annealing process. The post‐annealed MSM a‐Ga2O3 SBPDs exhibit superhigh sensitivity of 733 A/W and high response speed of 18 ms, giving a high gain‐bandwidth product over 104 at 5 V. The SBPDs also show ultrahigh photo‐to‐dark current ratio of 3.9 × 107. Additionally, the PDs demonstrate super‐high specific detectivity of 3.9 × 1016 Jones owing to the extremely low noise down to 3.5 fW Hz−1/2, suggesting high signal‐to‐noise ratio. Underlying mechanism for such superior photoelectric properties is revealed by Kelvin probe force microscopy and first principles calculation. Furthermore, for the first time, a large‐scale, high‐uniformity 32 × 32 image sensor array based on the post‐annealed a‐Ga2O3 SBPDs is fabricated. Clear image of target object with high contrast can be obtained thanks to the high sensitivity and uniformity of the array. These results demonstrate the feasibility and practicality of the Ga2O3 PDs for applications in solar‐blind imaging, environmental monitoring, artificial intelligence and machine vision. [ABSTRACT FROM AUTHOR]

We demonstrated a resistive random access memory (RRAM) based embedded non-volatile memory (e-NVM) solution integrated in the 0.13 $\mu $ m partially depleted silicon on insulator (PD-SOI) process. The memory devices show excellent reliability. It has good endurance up to 5 electrical cycles without any degradation in low resistance state (LRS) and high resistance state (HRS). It can retain the data up to 5 s even at 125 °C. Both the LRS and HRS show little variation. After $\gamma $ -ray radiation with various total ionizing doses (TIDs), the memory characteristics of the device including resistance states, set/reset voltages are not significantly degraded, suggesting good anti-radiation capability. The proposed 1T1R device integrated in SOI process provides a potential candidate for those applications in radiation environments. [ABSTRACT FROM AUTHOR]

The 3D crossbar arrays provide a cost-effective approach for high-density integration of resistive switching random-access memory (RRAM). A selector device or self-selective cells can be used to inhibit the sneaking current from the unselected cells. The coexistence of memory switching (MS) with inherent nonlinearity and threshold switching (TS) with high current density in an individual material system will lead to technological benefits for memory integration and neuromorphic computing. However, the reported conductive filament (CF)-type MS and TS combining devices cannot meet the requirements for practical applications, as these devices lack built-in nonlinearity in memory mode and display low current density and large relaxing time in the selector mode. In this letter, we report a 3D TiN/TiO2/NbOX/Pt device with MS and TS before and after the forming processes. In the MS mode, this device shows >50 nonlinearity, a 100 ON/OFF ratio, non-volatility, and stable homogeneous switching due to vacancy redistribution. In the TS mode, owing to the metal–insulator transition, a high ON-state current (1.6 MA/cm 2), high switching speed (<40 ns), and low relaxation time (<50 ns) are observed. [ABSTRACT FROM AUTHOR]

Ferroelectric materials with a perovskite structure have various shortcomings, including poor Si compatibility, large physical thickness, and small bandgap. HfO2-based ferroelectric materials provide a new solution for ferroelectric semiconductor devices. HfO2-ZrO2 solid solution (HZO) thin films have been widely studied due to their low crystallization temperature and wide stoichiometric range. Considering its low cost and flexible deposition conditions, the sputtering technique is a useful method for HZO deposition. However, sputtered HZO ferroelectric films have been rarely reported, and the composition effect on the ferroelectric properties of HfXZr1−XO2 thin films is still unclear. In this letter, sputtered HfXZr1−XO2 thin films were studied with different Zr contents (from 12.49 to 20.34 mol%) by varying the sputtering power ratio of ZrO2 to HfO2. We found that the dopant concentration with the best ferroelectric properties in the HfXZr1−XO2 system is ~15–16 mol%, which is much lower than that in the ALD-based HZO film. First-principle calculation shows that oxygen vacancies doped in the HZO film lead to a change in the Helmholtz free energy of different phases, which affected the optimal Zr concentration for the largest ferroelectric polarization. [ABSTRACT FROM AUTHOR]

Resistance fluctuation is a big concern of resistive random access memory (RRAM) since it has close connection with chip design. In this work, resistance fluctuation of RRAM devices fabricated on 28-nm CMOS platform is investigated systematically by means of low frequency noise measurement. The relationship among resistance fluctuation and resistance states/reading time/ reading conditions is quantitatively analyzed. We show that the resistance broadening has positive correlation with resistance states and reading time. Meanwhile, for reading voltage, it should be selected below 0.3V in order to avoid resistance degradation. Based on this quantitative analysis, an analytical formula to predict the resistance spread as a function of time, resistance, read voltage is derived. This prediction result provides a valuable guideline for selection of resistance working range and read pulse parameter, which is of great importance for future circuit design. [ABSTRACT FROM AUTHOR]

In oxide-based resistive switching memory (OxRAM), due to the existence of oxygen ions, electron-induced random telegraph noise (e-RTN) and oxygen ion-induced RTN (GR-RTN) coexist and cannot be distinguished directly from the current levels in typical two-level RTN signals. Thus, the accurate extraction of the trap location and energy level (${X}_{T}$ , ${E}_{T}$) based on the time constants from e-RTN is hindered, which impedes the further investigation of reliability. In this work, three-level RTN in TMOx-based OxRAM was investigated. GR-RTN and e-RTN were both observed and can be distinguished clearly by the comparison of the three discrete current levels. Also, especially for e-RTN, we discussed the bias dependency of time constants of the three-level e-RTN, and the vertical location and energy level of the trap corresponding to this three-level e-RTN were finally extracted. This extraction method after selecting e-RTN from all RTN signals provides a more accurate characterization result of the trap and will be helpful to the investigation of the reliability in OxRAM devices. [ABSTRACT FROM AUTHOR]

Self-selective cells (SSCs) with built-in nonlinearity provide a promising solution for overcoming the leakage current issue of 3-D vertical resistive random access memory arrays. However, deep understanding of the switching mechanism of the SSC device is still lacking, hindering the effective improvement of the device performance. In this letter, we investigated the switching mechanism of the TaOx/HfO2 SSC device by probing the trap profiles with RTN measurements. Both the vertical locations and energy levels ( ${X} _{T}$ , $\text{E}_{T}$ ) of defects in the HRS and LRS could be calculated by the bias-dependence of the capture and emission time constants ( $\tau _{e}$ and $\tau _{c}$ ). Using the comparison of the defect profiles before and after the resistive switching, an active region in the TaOx layer adjacent to the HfO2 layer could be clearly identified. Based on these results, a clear picture of resistive switching in the TaOx/HfO2 SSC was obtained. [ABSTRACT FROM AUTHOR]

Read error caused by resistance change or fluctuation occurred in read operation is a critical issue of resistive random access memory (RRAM) and needs to be paid special attention in chip design. In this letter, we investigated the resistance fluctuation of an RRAM device fabricated on 28-nm CMOS platform, with statistical data collected on the sub-array of 1-Mb macro. The evolution of resistance states in various resistance ranges was traced under continuous read pulse with varied heights. The resistance states were found either randomly fluctuated or degraded over several orders of magnitudes, depending on the read voltage. The random telegraph noise measurement shows electron capture and emission at trap sites near or inside of the filament path acts as the major cause of resistance fluctuation, whereas atomic defects generation in the current transport path as the read voltage higher than 0.7-V results in large range variation. The results of this work provide a valuable guideline to reduce the bit error rate of RRAM chip. [ABSTRACT FROM AUTHOR]

The self-rectifying resistive-switching (RS) device is one of the most promising solutions to overcome the sneaking current issue in a 3D vertical crossbar array. In this letter, we report a CMOS-compatible, forming-free, self-rectifying resistive random access memory device with high uniformity and low operation voltage (<3V) for embedded memory application. Thanks to the low read voltage, this device shows robust read disturbance (>109) characteristics. After introducing a 3-nm HfO2 thin film between Pd and WOx layer, Schottky contact of Pd/HfO2 was formed, which resulted in rectifying property. The HfO2 layer also served as an oxygen reservoir for RS in WOx layer. This novel memory device with excellent performance is a promising candidate for future high density embedded memory application. [ABSTRACT FROM AUTHOR]

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system's operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications. [ABSTRACT FROM AUTHOR]

Bi-layer structure has been widely adopted to improve the reliability of the conductive bridge random access memory (CBRAM). In this work, we proposed a convenient and economical solution to achieve a Ta2O5/TaOx bi-layer structure by using a low-temperature annealing process. The addition of a TaOx layer acted as an external resistance suppressing the overflow current during set programming, thus achieving the self-compliance switching. As a result, the distributions of high-resistance states and low-resistance states are improved due to the suppression of the overset phenomenon. In addition, the LRS retention of the CBRAM is obviously enhanced due to the recovery of defects in the switching film. This work provides a simple and economical method to improve the reliability of CBRAM. [ABSTRACT FROM AUTHOR]

The growing demand for scalable solar-blind image sensors with remarkable photosensitive properties has stimulated the research on more advanced solar-blind photodetector (SBPD) arrays. In this work, the authors demonstrate ultrahigh-performance metal-semiconductor-metal (MSM) SBPDs based on amorphous (a-) Ga 2 O 3 via a post-annealing process. The post-annealed MSM a-Ga 2 O 3 SBPDs exhibit superhigh sensitivity of 733 A/W and high response speed of 18 ms, giving a high gain-bandwidth product over 10 4 at 5 V. The SBPDs also show ultrahigh photo-to-dark current ratio of 3.9 × 10 7 . Additionally, the PDs demonstrate super-high specific detectivity of 3.9 × 10 16 Jones owing to the extremely low noise down to 3.5 fW Hz -1/2 , suggesting high signal-to-noise ratio. Underlying mechanism for such superior photoelectric properties is revealed by Kelvin probe force microscopy and first principles calculation. Furthermore, for the first time, a large-scale, high-uniformity 32 × 32 image sensor array based on the post-annealed a-Ga 2 O 3 SBPDs is fabricated. Clear image of target object with high contrast can be obtained thanks to the high sensitivity and uniformity of the array. These results demonstrate the feasibility and practicality of the Ga 2 O 3 PDs for applications in solar-blind imaging, environmental monitoring, artificial intelligence and machine vision., (© 2021 The Authors. Advanced Science published by Wiley-VCH GmbH.)