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Abstract High-dimensional quantum information processing has emerged as a promising avenue to transcend hardware limitations and advance the frontiers of quantum technologies. Harnessing the untapped potential of the so-called qudits necessitates the development of quantum protocols beyond the established qubit methodologies. Here, we present a robust, hardware-efficient, and scalable approach for operating multidimensional solid-state systems using Raman-assisted two-photon interactions. We then utilize them to construct extensible multi-qubit operations, realize highly entangled multidimensional states including atomic squeezed states and Schrödinger cat states, and implement programmable entanglement distribution along a qudit array. Our work illuminates the quantum electrodynamics of strongly driven multi-qudit systems and provides the experimental foundation for the future development of high-dimensional quantum applications such as quantum sensing and fault-tolerant quantum computing.

Abstract The quantum computation of molecular response properties on near-term quantum hardware is a topic of substantial interest. Computing these properties directly in the frequency domain is desirable, but the circuits require large depth if the typical hardware gate set consisting of single- and two-qubit gates is used. While high-fidelity multipartite gates have been reported recently, their integration into quantum simulation and the demonstration of improved accuracy of the observable properties remains to be shown. Here, we report the application of a high-fidelity multipartite gate, the iToffoli gate, to the computation of frequency-domain response properties of diatomic molecules. The iToffoli gate enables a ~50% reduction in circuit depth and ~40% reduction in circuit execution time compared to the traditional gate set. We show that the molecular properties obtained with the iToffoli gate exhibit comparable or better agreement with theory than those obtained with the native CZ gates. Our work is among the first demonstrations of the practical usage of a native multi-qubit gate in quantum simulation, with diverse potential applications to near-term quantum computation.

Quantum-limited Josephson parametric amplifiers play a pivotal role in advancing the field of circuit quantum electrodynamics by enabling the fast and high-fidelity measurement of weak microwave signals. Therefore, it is necessary to develop robust parametric amplifiers with low noise, broad bandwidth, and reduced design complexity for microwave detection. However, current broadband parametric amplifiers either have degraded noise performance or rely on complex designs. Here, we present a device based on the broadband impedance-transformed Josephson parametric amplifier that integrates a hornlike coplanar waveguide transmission line, which significantly decreases the design and fabrication complexity while keeping comparable performance. The device shows an instantaneous bandwidth of 700 (200) MHz for 15 (20) dB gain with an average input saturation power of −110 dBm and near quantum-limited added noise. The operating frequency can be tuned over 1.4 GHz using an external flux bias. We further demonstrate the negligible backaction from our device on a transmon qubit. The amplification performance and simplicity of our device promise its wide adaptation in quantum metrology, quantum communication, and quantum information processing.

Abstract Contemporary methods for benchmarking noisy quantum processors typically measure average error rates or process infidelities. However, thresholds for fault-tolerant quantum error correction are given in terms of worst-case error rates—defined via the diamond norm—which can differ from average error rates by orders of magnitude. One method for resolving this discrepancy is to randomize the physical implementation of quantum gates, using techniques like randomized compiling (RC). In this work, we use gate set tomography to perform precision characterization of a set of two-qubit logic gates to study RC on a superconducting quantum processor. We find that, under RC, gate errors are accurately described by a stochastic Pauli noise model without coherent errors, and that spatially correlated coherent errors and non-Markovian errors are strongly suppressed. We further show that the average and worst-case error rates are equal for randomly compiled gates, and measure a maximum worst-case error of 0.0197(3) for our gate set. Our results show that randomized benchmarks are a viable route to both verifying that a quantum processor’s error rates are below a fault-tolerance threshold, and to bounding the failure rates of near-term algorithms, if—and only if—gates are implemented via randomization methods which tailor noise.

Using near-term quantum computers to achieve a quantum advantage requires efficient strategies to improve the performance of the noisy quantum devices presently available. We develop and experimentally validate two efficient error mitigation protocols named ``Noiseless Output Extrapolation" and ``Pauli Error Cancellation" that can drastically enhance the performance of quantum circuits composed of noisy cycles of gates. By combining popular mitigation strategies such as probabilistic error cancellation and noise amplification with efficient noise reconstruction methods, our protocols can mitigate a wide range of noise processes that do not satisfy the assumptions underlying existing mitigation protocols, including non-local and gate-dependent processes. We test our protocols on a four-qubit superconducting processor at the Advanced Quantum Testbed. We observe significant improvements in the performance of both structured and random circuits, with up to $86\%$ improvement in variation distance over the unmitigated outputs. Our experiments demonstrate the effectiveness of our protocols, as well as their practicality for current hardware platforms.

Abstract Ternary quantum information processing in superconducting devices poses a promising alternative to its more popular binary counterpart through larger, more connected computational spaces and proposed advantages in quantum simulation and error correction. Although generally operated as qubits, transmons have readily addressable higher levels, making them natural candidates for operation as quantum three-level systems (qutrits). Recent works in transmon devices have realized high fidelity single qutrit operation. Nonetheless, effectively engineering a high-fidelity two-qutrit entanglement remains a central challenge for realizing qutrit processing in a transmon device. In this work, we apply the differential AC Stark shift to implement a flexible, microwave-activated, and dynamic cross-Kerr entanglement between two fixed-frequency transmon qutrits, expanding on work performed for the Z Z interaction with transmon qubits. We then use this interaction to engineer efficient, high-fidelity qutrit CZ† and CZ gates, with estimated process fidelities of 97.3(1)% and 95.2(3)% respectively, a significant step forward for operating qutrits on a multi-transmon device.

Randomized benchmarking (RB) protocols are the most widely used methods for assessing the performance of quantum gates. However, the existing RB methods either do not scale to many qubits or cannot benchmark a universal gate set. Here, we introduce and demonstrate a technique for scalable RB of many universal and continuously parametrized gate sets, using a class of circuits called randomized mirror circuits. Our technique can be applied to a gate set containing an entangling Clifford gate and the set of arbitrary single-qubit gates, as well as gate sets containing controlled rotations about the Pauli axes. We use our technique to benchmark universal gate sets on four qubits of the Advanced Quantum Testbed, including a gate set containing a controlled-S gate and its inverse, and we investigate how the observed error rate is impacted by the inclusion of non-Clifford gates. Finally, we demonstrate that our technique scales to many qubits with experiments on a 27-qubit IBM Q processor. We use our technique to quantify the impact of crosstalk on this 27-qubit device, and we find that it contributes approximately 2/3 of the total error per gate in random many-qubit circuit layers.

It is for the first time that quantum simulation for high-energy physics (HEP) is studied in the U.S. decadal particle-physics community planning, and in fact until recently, this was not considered a mainstream topic in the community. This fact speaks of a remarkable rate of growth of this subfield over the past few years, stimulated by the impressive advancements in quantum information sciences (QIS) and associated technologies over the past decade, and the significant investment in this area by the government and private sectors in the U.S. and other countries. High-energy physicists have quickly identified problems of importance to our understanding of nature at the most fundamental level, from tiniest distances to cosmological extents, that are intractable with classical computers but may benefit from quantum advantage. They have initiated, and continue to carry out, a vigorous program in theory, algorithm, and hardware co-design for simulations of relevance to the HEP mission. This Roadmap is an attempt to bring this exciting and yet challenging area of research to the spotlight, and to elaborate on what the promises, requirements, challenges, and potential solutions are over the next decade and beyond.

As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large-scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system-level optimization. We design a modular field-programmable gate array (FPGA)-based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software. A prototype hardware module is assembled from several commercial off-the-shelf evaluation boards and in-house-developed circuit boards. Gateware and software are designed to implement basic qubit control and measurement protocols. System functionality and performance are demonstrated by performing qubit chip characterization, gate optimization, and randomized benchmarking sequences on a superconducting quantum processor operating at the Advanced Quantum Testbed at the Lawrence Berkeley National Laboratory. The single-qubit and two-qubit process fidelities are measured to be 0.9980 $\pm$ 0.0001 and 0.948 $\pm$ 0.004, respectively, by randomized benchmarking. With fast circuit sequence loading capability, the QubiC performs randomized compiling experiments efficiently and improves the feasibility of executing more complex algorithms.

The exploration of highly connected networks of qubits is invaluable for implementing various quantum algorithms and simulations, as it allows for entangling qubits with reduced circuit depth. Here, we demonstrate a multiqubit sideband tone-assisted Rabi-driven gate. Our scheme is inspired by the ion-qubit Mølmer-Sørensen gate and is mediated by a shared photonic mode and Rabi-driven superconducting qubits, which relaxes restrictions on qubit frequencies during fabrication and supports scalability. We achieve a two-qubit gate with a maximum state fidelity of 95% in 310 ns, a three-qubit gate with a state fidelity of 90.5% in 217 ns, and a four-qubit gate with a state fidelity of 66% in 200 ns. Furthermore, we develop a model of the gate that shows that the four-qubit gate is limited by shared resonator losses and the spread of qubit-resonator couplings, which must be addressed to reach high-fidelity operations.

Recent progress in noisy intermediate-scale quantum (NISQ) hardware shows that quantum devices may be able to tackle complex problems even without error correction. However, coherent errors due to the increased complexity of these devices is an outstanding issue. They can accumulate through a circuit, making their impact on algorithms hard to predict and mitigate. Iterative algorithms like quantum imaginary time evolution are susceptible to these errors. This article presents the combination of both noise tailoring using randomized compiling and error mitigation with purification. We also show that cycle benchmarking gives an estimate of the reliability of the purification. We apply this method to the quantum imaginary time evolution of a transverse field Ising model and report an energy estimation error and a ground-state infidelity both below 1%. Our methodology is general and can be used for other algorithms and platforms. We show how combining noise tailoring and error mitigation will push forward the performance of NISQ devices.

Transforming stand-alone qubits into a functional, general-purpose quantum processing unit requires an architecture where many-body quantum entanglement can be generated and controlled in a coherent, modular, and measurable fashion. Electronic circuits promise a well-developed pathway for large-scale integration once a mature library of quantum-compatible elements have been developed. In the domain of superconducting circuits, fluxonium has recently emerged as a promising qubit due to its high-coherence and large anharmonicity, yet its scalability has not been systematically explored. In this work, we present a blueprint for a high-performance fluxonium-based quantum processor that addresses the challenges of frequency crowding, and both quantum and classical crosstalk. The main ingredients of this architecture include high-anharmonicity circuits, multipath couplers to entangle qubits where spurious longitudinal coupling can be nulled, circuit designs that are compatible with multiplexed microwave circuitry, and strongly coupled readout channels that do not require complex, frequency-sculpted elements to maintain coherence. In addition, we explore robust and resource-efficient protocols for quantum logical operations, then perform numerical simulations to validate the expected performance of this proposed processor with respect to gate fidelity, fabrication yield, and logical error suppression. Lastly, we discuss practical considerations to implement the architecture and achieve the anticipated performance.

The SWAP network is a qubit routing sequence that can be used to efficiently execute the Quantum Approximate Optimization Algorithm (QAOA). Even with a minimally connected topology on an n-qubit processor, this routing sequence enables O(n^{2}) operations to execute in O(n) steps. In this work, we optimize the execution of SWAP networks for QAOA through two techniques. First, we take advantage of an overcomplete set of native hardware operations [including 150-ns controlled-π/2 phase gates with up to 99.67(1)% fidelity] to decompose the relevant quantum gates and SWAP networks in a manner which minimizes circuit depth and maximizes gate cancellation. Second, we introduce equivalent circuit averaging, which randomizes over degrees of freedom in the quantum circuit compilation to reduce the impact of systematic coherent errors. Our techniques are experimentally validated at the Advanced Quantum Testbed through the execution of QAOA circuits for finding the ground state of two- and four-node Sherrington-Kirkpatrick spin-glass models with various randomly sampled parameters. We observe a ∼60% average reduction in error (total variation distance) for QAOA of depth p=1 on four transmon qubits on a superconducting quantum processor.

Fixed-frequency superconducting quantum processors are one of the most mature quantum computing architectures with high-coherence qubits and simple controls. However, high-fidelity multiqubit gates pose tight requirements on individual qubit frequencies in these processors, and these constraints are difficult to satisfy when constructing larger processors due to the large dispersion in the fabrication of Josephson junctions. In this paper, we propose a mixed-integer-programming-based optimization approach that determines qubit frequencies to maximize the fabrication yield of quantum processors. We study traditional qubit and qutrit (three-level) architectures with cross-resonance interaction processors. We compare these architectures to a differential ac-Stark shift based on entanglement gates and show that our approach greatly improves the fabrication yield and also increases the scalability of these devices. Our approach is general and can be adapted to problems where one must avoid specific frequency collisions.

Materials imperfections in planar superconducting quantum circuits—in particular, two-level-system (TLS) defects—contribute significantly to decoherence, ultimately limiting the performance of quantum computation and sensing. The identification of specific parasitic layers and their associated loss contributions has, however, proven elusive. Using a combination of x-ray photoemission spectroscopy (XPS) and analytical scanning transmission electron microscopy (STEM), we determine the thickness, chemical composition, and location of the oxides present in niobium-on-silicon coplanar-waveguide (CPW) resonators and quantify their respective contributions to the measured single-photon quality factor (Q). Using selective chemical etching, we reduce first the substrate-air oxide then the metal-air oxide thickness, dramatically reducing both TLS (δ_{TLS}) and non-TLS (δ_{hi}) losses, resulting in a median Q value over 5×10^{6}, with individual devices approaching 6×10^{6}. We find that silicon surface oxides host 70% of TLS losses, with a δ_{TLS}:δ_{hi} loss-density ratio near 11:1. In contrast, niobium surface oxides host 77% of non-TLS losses, uniformly distributed within the oxide layer, with a δ_{TLS}:δ_{hi} loss-density ratio of 3:4 for the superconducting circuits investigated in this work. Only 7% of losses come from other sources, including the niobium-silicon interface, which is sufficiently clean in our devices to allow epitaxial Nb nucleation on Si. As we mitigate surface losses through selective modification of the interface dielectrics, we arrive in a regime where TLS losses are no longer dominant, which will allow other types of losses in superconducting circuits to be investigated in more detail, including nonequilibrium quasiparticles.

Crosstalk is a leading source of failure in multiqubit quantum information processors. It can arise from a wide range of disparate physical phenomena, and can introduce subtle correlations in the errors experienced by a device. Several hardware characterization protocols are able to detect the presence of crosstalk, but few provide sufficient information to distinguish various crosstalk errors from one another. In this article we describe how gate set tomography, a protocol for detailed characterization of quantum operations, can be used to identify and characterize crosstalk errors in quantum information processors. We demonstrate our methods on a two-qubit trapped-ion processor and a two-qubit subsystem of a superconducting transmon processor.