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In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which in their turn are obtained from the so-called Ward-Dutton charge partitioning scheme. For devices with a laterally nonuniform channel doping profile, however, it is shown in this paper that no terminal charges exist from which the capacitances can be derived. Instead, for such devices, a new model is presented for the capacitances themselves. Furthermore, a method is given to incorporate such a capacitance model into circuit simulators, which are traditionally based on terminal charge models. Comparison with two-dimensional device simulations and a segmentation model shows that for a constant mobility, the new capacitance model provides an accurate description for a MOSFET with a laterally diffused channel doping profile. Through a comparison with high-frequency measurements, the agreement between model and experimental results is discussed.

This paper presents a general weak nonlinearity model that can be used to model, analyze and describe the distortion behavior of various low noise amplifier topologies in both narrowband and wideband applications. Represented by compact closed-form expressions our model can be easily utilized by both circuit designers and LNA design automation algorithms. Simulations for three LNA topologies at different operating conditions show that the model describes IM components with an error lower than 0.1% and a one order of magnitude faster response time. The model also indicates that for narrowband IM2@w1-w2 all the nonlinear capacitances can be neglected while for narrowband IM3 the nonlinear capacitances at the drainterminal can be neglected.

In this paper, a small-signal MOSFET model is described, which takes the local effects of both velocity saturation and transverse mobility reduction into account. The model is based on the PSP model and is valid for both quasi-static and nonquasi-static (NQS) operations. Recently, it has been found that, in the presence of velocity saturation, the low-frequency capacitances cannot be determined from the Ward-Dutton charge-partitioning scheme. By use of the small-signal model developed in this paper, it is demonstrated that, in the presence of velocity saturation, no terminal drain and source charges exist, from which the capacitances can be derived. The small-signal model enables the determination of the correct capacitive behavior in the presence of velocity saturation. Furthermore, it is demonstrated how the small-signal model can be used to determine the number of collocation points needed in the large-signal NQS PSP model. Finally, inclusion of the local variation of mobility reduction due to the vertical electrical fields provides insight into the approach commonly applied in compact modeling, where these fields are replaced by global ones depending on the terminal voltages only.

We demonstrate that by careful layout optimisation, particularly aimed at reducing the effective gate resistance, a record high maximum oscillation frequency fmax of 150 GHz can be obtained for an industrial 0.18 μm CMOS process showing a cut-off frequency fT of 70 GHz. A very low minimum noise figure and good suppression of the substrate noise using a guard-ring is also shown.