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This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a concurrent temperature estimate for dynamic power and temperature management. This sensor occupies an area of 0.01 mm2 in a 0.13-μm CMOS technology. With a simplified one-point calibration and a response time of 80 ns, it shows improvements in input dynamic range by ten times, response time by six times, and sensitivity by three times over previous such sensors. A compact low-power current reference with a 3-σmax TC of 127 ppm/°C and a line regulation of 1%/V is also presented, which is used in a replica-structure-based online calibration scheme, resulting in improved tolerance to variations in process, voltage, and temperature (PVT) and degradation due to supply noise as well as aging. [ABSTRACT FROM PUBLISHER]

A new approach for protecting sensitive receivers through large attenuation and its realization on-chip is presented for the first time. This paper demonstrates the use of absorptive bandstop filters that gives anomalously deep notches for a given quality factor. This approach is used in a fabricated design example to isolate a sensitive wideband LNA from interference in 45-nm SOI complementary metaloxide-semiconductor (CMOS). For reconfigurable RF front-ends, a frequency-agile design is newly developed with Q tunable resonators because an absorptive bandstop filter must balance both intrinsic Q of the resonators and the resonant frequency of the filter. Therefore, the design requires variable resistors, variable capacitors, and intimate coupling of inductors of disparate values. The layout of overlapping inductors on closely spaced metal layers is required for proper absorptive properties. The size of one filter presented in this paper is 310 by 340 μm, making it the smallest absorptive bandstop filter demonstrated so far. Despite using small-size, on-chip low-Q resonators in the bandstop filter design, an attenuation level from 31 to 63 dB and a frequency tuning range from 2.9 to 4.3 GHz are achieved with potential to suppress potential interference or an image frequency signal. [ABSTRACT FROM AUTHOR]

A new design technique that improves operating speed of true single-phase clock-based (TSPC) prescalers is presented. We implement dual-modulus prescalers without using any extra logic gates by exploiting the behavior of the second branch in a TSPC flip-flop. The proposed design technique is applied to \div2/3 and \div3/4 prescalers, and their performances are compared with previous work. Implemented in a 130-nm CMOS technology and compared at same process–voltage–temperature conditions, the maximum speed of the \div2/3 prescaler reaches 88% of the maximum operating frequency of a single TSPC flip-flop, and the \div3/4 prescaler reaches 75%. In addition, the proposed divide-by-3 prescaler is able to work almost at the speed of the single TSPC flip-flop. A frequency divider that provides dividing ratios of 7, 8, and 9 is implemented as a part of a 3.4–5-GHz integer- N phase-locked loop in a 130-nm CMOS technology. Simulation and measurement results demonstrate high-speed, low-power, and multiple division ratio capabilities of the proposed technique. [ABSTRACT FROM PUBLISHER]

A gm-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of gm-boosting as in inductively degenerated topology. The gain of the LNA increases by the Q-factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the gm-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of -11 dBm while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 mm² in 0.13-μm CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB. [ABSTRACT FROM AUTHOR]

A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10-8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 Ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks. [ABSTRACT FROM AUTHOR]

In this paper, we evaluate the high-frequency performance limitations of traditional LC voltage-controlled oscillators (VCOs) that use a cross-coupled negative resistance cell and propose a new topology that overcomes these limitations. The proposed cell is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties combined with its small effective capacitance enable low-power low-noise high-frequency VCO implementations. The proposed topology is demonstrated through a 20-GHz fully integrated LC VCO implemented in the IBM SiGe 0.25-μm BiCMOS process. A comparison of its figure of merit with previously reported 20-GHz VCOs shows the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This letter analyzes the implementation issues related to coherent receivers for UWB impulse radio with a special emphasis on timing and jitter problems. We propose a new jitter tolerant receiver design that is easy to implement. Analytical BER analysis and simulations verify that the performance of the proposed receiver is comparable to that of a correlator-based receiver that includes jitter. The new design is a promising candidate for low-cost low-power UWB IR receiver implementations. [ABSTRACT FROM PUBLISHER]

Editor's note:Despite their inherent self-healing nature, noise (jitter) in phase-locked loops is sensitive to process and environmental variation. This article discusses automatic frequency calibration and amplitude control techniques that rely on a negative feedback loop with a large emphasis on digitally assisted calibration.—Rahul Rao, IBM [ABSTRACT FROM PUBLISHER]