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The evolution of super-resolution (SR) technology has seen significant advancements through the adoption of deep learning methods. However, the deployment of such models by resource-constrained devices necessitates models that not only perform efficiently, but also conserve computational resources. Binary neural networks (BNNs) offer a promising solution by minimizing the data precision to binary levels, thus reducing the computational complexity and memory requirements. However, for BNNs, an effective architecture is essential due to their inherent limitations in representing information. Designing such architectures traditionally requires extensive computational resources and time. With the advancement in neural architecture search (NAS), differentiable NAS has emerged as an attractive solution for efficiently crafting network structures. In this paper, we introduce a novel and efficient binary network search method tailored for image super-resolution tasks. We adapt the search space specifically for super resolution to ensure it is optimally suited for the requirements of such tasks. Furthermore, we incorporate Libra Parameter Binarization (Libra-PB) to maximize information retention during forward propagation. Our experimental results demonstrate that the network structures generated by our method require only a third of the parameters, compared to conventional methods, and yet deliver comparable performance. [ABSTRACT FROM AUTHOR]

Binarization is an extreme quantization technique that is attracting research in the Internet of Things (IoT) field, as it radically reduces the memory footprint of deep neural networks without a correspondingly significant accuracy drop. To support the effective deployment of Binarized Neural Networks (BNNs), we propose CBin-NN, a library of layer operators that allows the building of simple yet flexible convolutional neural networks (CNNs) with binary weights and activations. CBin-NN is platform-independent and is thus portable to virtually any software-programmable device. Experimental analysis on the CIFAR-10 dataset shows that our library, compared to a set of state-of-the-art inference engines, speeds up inference by 3.6 times and reduces the memory required to store model weights and activations by 7.5 times and 28 times, respectively, at the cost of slightly lower accuracy (2.5%). An ablation study stresses the importance of a Quantized Input Quantized Kernel Convolution layer to improve accuracy and reduce latency at the cost of a slight increase in model size. [ABSTRACT FROM AUTHOR]

In the realm of neuromorphic computing, integrating Binary Neural Networks (BNN) with non‐volatile memory based on emerging materials can be a promising avenue for introducing novel functionalities. This study underscores the viability of lead‐free, air‐stable Cs2SnI6 (CSI) based resistive random access memory (RRAM) devices as synaptic weights in neuromorphic architectures, specifically for BNNs applications. Herein, hydrothermally synthesized CSI perovskites are explored as a resistive layer in RRAM devices either on the rigid or flexible substrate, highlighting reproducible multibit switching with self‐compliance, low‐ resistance‐state (LRS) variations, a decent On/Off ratio(or retention) of ≈103(or 104 s), and endurance exceeding 300 cycles. Moreover, a comprehensive evaluation with the 32 × 32 × 3 RGB CIFAR‐10 dataset reveals that binary convolutional neural networks (BCNN) trained solely on binary weight values can achieve competitive rates of accuracy comparable to those of their analog weight counterparts. These findings highlight the dominance of the LRS for CSI RRAM with self‐compliance in a weighted configuration and minimal influence of the high resistance state despite substantial fluctuations for flexible CSI RRAM under varying bending radii. With its unique electrical switching capabilities, the CSI RRAM is highly anticipated to emerge as a promising candidate for embedded AI systems, especially in IoT devices and wearables. [ABSTRACT FROM AUTHOR]

In this article, an electrostatically-actuated NEMS XOR gate is proposed based on photonic crystals for hardware implementation of binary neural networks. The device includes a 2D photonic crystal which is set on a movable electrode to implement the XOR logic using the transmission of specific wavelengths to the output. This design represents the importance of the proposed structure in which the logic gate operation is not dependent on the contact of its conductive layers. Consequently, one of the major issues in MEMS-based logic gates, which is due to the contact of the operating electrodes and may cause stiction problem, reducing the reliability of the system, can be tackled by the present approach. Furthermore, according to the simulation results, the functional characteristics of the present NEMS XOR gate are obtained as follows: pull-in voltage of Vp = 8V, operating voltage of Vo = 10V and switching time of ts = 4 μs. The results also show that the proposed design provides a classification error rate of between 1% to 12%, while used in neural network implementation. This error can be negligible compared to the state-of-the-art designs in neural network implementation. These appropriate parameters of the present NEMS gate make it a promising choice for the implementation of neural networks with a high network accuracy even in the presence of significant process variations. [ABSTRACT FROM AUTHOR]

Neural architecture search (NAS) proves to be among the effective approaches for many tasks by generating an application-adaptive neural architecture, which is still challenged by high computational cost and memory consumption. At the same time, 1-bit convolutional neural networks (CNNs) with binary weights and activations show their potential for resource-limited embedded devices. One natural approach is to use 1-bit CNNs to reduce the computation and memory cost of NAS by taking advantage of the strengths of each in a unified framework, while searching the 1-bit CNNs is more challenging due to the more complicated processes involved. In this paper, we introduce Discrepant Child–Parent Neural Architecture Search (DCP–NAS) to efficiently search 1-bit CNNs, based on a new framework of searching the 1-bit model (Child) under the supervision of a real-valued model (Parent). Particularly, we first utilize a Parent model to calculate a tangent direction, based on which the tangent propagation method is introduced to search the optimized 1-bit Child. We further observe a coupling relationship between the weights and architecture parameters existing in such differentiable frameworks. To address the issue, we propose a decoupled optimization method to search an optimized architecture. Extensive experiments demonstrate that our DCP–NAS achieves much better results than prior arts on both CIFAR-10 and ImageNet datasets. In particular, the backbones achieved by our DCP–NAS achieve strong generalization performance on person re-identification and object detection. [ABSTRACT FROM AUTHOR]

The ever-growing computational demands of increasingly complex machine learning models frequently necessitate the use of powerful cloud-based infrastructure for their training. Binary neural networks are known to be promising candidates for on-device inference due to their extreme compute and memory savings over higher-precision alternatives. However, their existing training methods require the concurrent storage of high-precision activations for all layers, generally making learning on memory-constrained devices infeasible. In this article, we demonstrate that the backward propagation operations needed for binary neural network training are strongly robust to quantization, thereby making on-the-edge learning with modern models a practical proposition. We introduce a low-cost binary neural network training strategy exhibiting sizable memory footprint reductions while inducing little to no accuracy loss vs Courbariaux & Bengio's standard approach. These decreases are primarily enabled through the retention of activations exclusively in binary format. Against the latter algorithm, our drop-in replacement sees memory requirement reductions of 3-5x, while reaching similar test accuracy (±2 pp) in comparable time, across a range of small-scale models trained to classify popular datasets. We also demonstrate from-scratch ImageNet training of binarized ResNet-18, achieving a 3.78x memory reduction. Our work is open-source, and includes the Raspberry Pi-targeted prototype we used to verify our modeled memory decreases and capture the associated energy drops. Such savings will allow for unnecessary cloud offloading to be avoided, reducing latency, increasing energy efficiency, and safeguarding end-user privacy. [ABSTRACT FROM AUTHOR]

Deep learning (DL) has recently changed the development of intelligent systems and is widely adopted in many real-life applications. Despite their various benefits and potentials, there is a high demand for DL processing in different computationally limited and energy-constrained devices. It is natural to study game-changing technologies such as Binary Neural Networks (BNN) to increase DL capabilities. Recently remarkable progress has been made in BNN since they can be implemented and embedded on tiny restricted devices and save a significant amount of storage, computation cost, and energy consumption. However, nearly all BNN acts trade with extra memory, computation cost, and higher performance. This article provides a complete overview of recent developments in BNN. This article focuses exclusively on 1-bit activations and weights 1-bit convolution networks, contrary to previous surveys in which low-bit works are mixed in. It conducted a complete investigation of BNN's development—from their predecessors to the latest BNN algorithms/techniques, presenting a broad design pipeline and discussing each module's variants. Along the way, it examines BNN (a) purpose: their early successes and challenges; (b) BNN optimization: selected representative works that contain essential optimization techniques; (c) deployment: open-source frameworks for BNN modeling and development; (d) terminal: efficient computing architectures and devices for BNN and (e) applications: diverse applications with BNN. Moreover, this paper discusses potential directions and future research opportunities in each section. [ABSTRACT FROM AUTHOR]

Plant disease control has long been a critical issue in agricultural production and relies heavily on the identification of plant diseases, but traditional disease identification requires extensive experience. Most of the existing deep learning-based plant disease classification methods run on high-performance devices to meet the requirements for classification accuracy. However, agricultural applications have strict cost control and cannot be widely promoted. This paper presents a novel method for plant disease classification using a binary neural network with dual attention (DABNN), which can save computational resources and accelerate by using binary neural networks, and introduces a dual-attention mechanism to improve the accuracy of classification. To evaluate the effectiveness of our proposed approach, we conduct experiments on the PlantVillage dataset, which includes a range of diseases. The F 1 s c o r e and A c c u r a c y of our method reach 99.39% and 99.4%, respectively. Meanwhile, compared to AlexNet and VGG16, the C o m p u t a t i o n a l c o m p l e x i t y of our method is reduced by 72.3% and 98.7%, respectively. The P a r a m s s i z e of our algorithm is 5.4% of AlexNet and 2.3% of VGG16. The experimental results show that DABNN can identify various diseases effectively and accurately. [ABSTRACT FROM AUTHOR]

The evolution of super-resolution (SR) technology has seen significant advancements through the adoption of deep learning methods. However, the deployment of such models by resource-constrained devices necessitates models that not only perform efficiently, but also conserve computational resources. Binary neural networks (BNNs) offer a promising solution by minimizing the data precision to binary levels, thus reducing the computational complexity and memory requirements. However, for BNNs, an effective architecture is essential due to their inherent limitations in representing information. Designing such architectures traditionally requires extensive computational resources and time. With the advancement in neural architecture search (NAS), differentiable NAS has emerged as an attractive solution for efficiently crafting network structures. In this paper, we introduce a novel and efficient binary network search method tailored for image super-resolution tasks. We adapt the search space specifically for super resolution to ensure it is optimally suited for the requirements of such tasks. Furthermore, we incorporate Libra Parameter Binarization (Libra-PB) to maximize information retention during forward propagation. Our experimental results demonstrate that the network structures generated by our method require only a third of the parameters, compared to conventional methods, and yet deliver comparable performance.

This paper proposes a Reconfigurable In-Memory Advance Computing architecture using a novel 10 SRAM cell. In addition to basic logic operations, the proposed R-InMAC can also implement complex Boolean computing operations such as binary addition/subtraction, binary-to-gray, gray-to-binary conversion, 2's complement, less/greater than, and increment/decrement. Furthermore, content addressable memory (CAM) operation to search a binary string in a memory array is also proposed efficiently. It can search true and complementary data strings in a single cycle. The proposed R-InMAC architecture's reconfigurability allows it to be configured according to the needed operation and bit precision, making it ideal and energy-efficient. In addition, compared to the standard SRAM cells, the proposed 10T cell is suited for implementing the XNOR-based binary convolution operation required in Binary Neural Networks (BNNs) with improved latency of 58.89%. The optimized full adder of the proposed R-InMAC shows decrement in the area by 40%, static power by 28%, dynamic power by 55.2%, and latency by 25.3% as compared to conventional designs, making this work a promising candidate for modern edge AI compute in-memory systems. [ABSTRACT FROM AUTHOR]

This study aims to leverage Binary Neural Networks (BNN) to learn binary hash codes for efficient person re-identification (ReID). BNNs, which use binary weights and activations, show promise in speeding up the inference time in deep models. However, BNNs typically suffer from performance degradation mainly due to the discontinuity of the binarization operation. Proxy functions have been proposed to calculate the gradients in the backward propagation, but they lead to the gradient mismatch problem. In this study, we propose to address the gradient mismatch problem by designing a multi-branch ensemble model consisting of many weak hash code learners. Specifically, our design aggregates the gradients from multiple branches, which allows a better approximation of the gradients and regularizes the network. Our model adds little computational cost to the baseline BNN since a vast amount of network parameters are shared between the weak learners. Combining the efficiency of the BNNs and hash code learning, we obtain an effective ensemble model which is efficient both in feature extraction and ranking phases. Our experiments demonstrate that the proposed model outperforms a single BNN by more than %20 using nearly the same amount of floating point operations. Moreover, the proposed model outperforms a conventional ensemble of BNN by more than %7 while being nearly 10x and 2x more efficient in terms of CPU consumption and memory footprint, respectively. We explore the performance of BNNs for efficient person ReID as one of the first systems available in the literature. Moreover, we adopt the proposed ensemble model for further validation of the image classification task and observe that our method effectively regularizes BNNs, providing robustness to hyperparameter selection and producing more consistent results under different settings.

This paper presents an extensive literature review on Binary Neural Network (BNN). BNN utilizes binary weights and activation function parameters to substitute the full-precision values. In digital implementations, BNN replaces the complex calculations of Convolutional Neural Networks (CNNs) with simple bitwise operations. BNN optimizes large computation and memory storage requirements, which leads to less area and power consumption compared to full-precision models. Although there are many advantages of BNN, the binarization process has a significant impact on the performance and accuracy of the generated models. To reflect the state-of-the-art in BNN and explore how to develop and improve BNN-based models, we conduct a systematic literature review on BNN with data extracted from 239 research studies. Our review discusses various BNN architectures and the optimization approaches developed to improve their performance. There are three main research directions in BNN: accuracy optimization, compression optimization, and acceleration optimization. The accuracy optimization approaches include quantization error reduction, special regularization, gradient error minimization, and network structure. The compression optimization approaches combine fractional BNN and pruning. The acceleration optimization approaches comprise computing in-memory, FPGA-based implementations, and ASIC-based implementations. At the end of our review, we present a comprehensive analysis of BNN applications and their evaluation metrics. Also, we shed some light on the most common BNN challenges and the future research trends of BNN.

The outputs of deep hash network (DHN) are binary codes, so DHN has high retrieval efficiency in matching phase and can be used for high-speed palmprint recognition, which is a promising biometric modality. In this paper, the templates and network parameters are both quantized for fast and light-weight palmprint recognition. The parameters of DHN are binarized to compress the network weight and accelerate the speed. To avoid accuracy degradation caused by quantization, mutual information is leveraged to optimize the ambiguity in Hamming space to obtain a tri-valued hash code as a palmprint template. Kleene Logic's tri-valued Hamming distance measures the dissimilarity between palmprint templates. The ablation experiments are tested on the binarization of the network parameter, and the normalization and trivialization of the deep hash output value. The sufficient experiments conducted on several contact and contactless palmprint datasets confirm the multiple advantages of our method. [ABSTRACT FROM AUTHOR]

As the scales of neural networks increase, techniques that enable them to run with low computational cost and energy efficiency are required. From such demands, various efficient neural network paradigms, such as spiking neural networks (SNNs) or binary neural networks (BNNs), have been proposed. However, they have sticky drawbacks, such as degraded inference accuracy and latency. To solve these problems, we propose a single-step spiking neural network (S 3 NN), an energy-efficient neural network with low computational cost and high precision. The proposed S 3 NN processes the information between hidden layers by spikes as SNNs. Nevertheless, it has no temporal dimension so that there is no latency within training and inference phases as BNNs. Thus, the proposed S 3 NN has a lower computational cost than SNNs that require time-series processing. However, S 3 NN cannot adopt naïve backpropagation algorithms due to the non-differentiability nature of spikes. We deduce a suitable neuron model by reducing the surrogate gradient for multi-time step SNNs to a single-time step. We experimentally demonstrated that the obtained surrogate gradient allows S 3 NN to be trained appropriately. We also showed that the proposed S 3 NN could achieve comparable accuracy to full-precision networks while being highly energy-efficient. [ABSTRACT FROM AUTHOR]

Model binarization is an effective method of compressing neural networks and accelerating their inference process, which enables state-of-the-art models to run on resource-limited devices. Recently, advanced binarization methods have been greatly improved by minimizing the quantization error directly in the forward process. However, a significant performance gap still exists between the 1-bit model and the 32-bit one. The empirical study shows that binarization causes a great loss of information in the forward and backward propagation which harms the performance of binary neural networks (BNNs). We present a novel distribution-sensitive information retention network (DIR-Net) that retains the information in the forward and backward propagation by improving internal propagation and introducing external representations. The DIR-Net mainly relies on three technical contributions: (1) Information Maximized Binarization (IMB): minimizing the information loss and the binarization error of weights/activations simultaneously by weight balance and standardization; (2) Distribution-sensitive Two-stage Estimator (DTE): retaining the information of gradients by distribution-sensitive soft approximation by jointly considering the updating capability and accurate gradient; (3) Representation-align Binarization-aware Distillation (RBD): retaining the representation information by distilling the representations between full-precision and binarized networks. The DIR-Net investigates both forward and backward processes of BNNs from the unified information perspective, thereby providing new insight into the mechanism of network binarization. The three techniques in our DIR-Net are versatile and effective and can be applied in various structures to improve BNNs. Comprehensive experiments on the image classification and objective detection tasks show that our DIR-Net consistently outperforms the state-of-the-art binarization approaches under mainstream and compact architectures, such as ResNet, VGG, EfficientNet, DARTS, and MobileNet. Additionally, we conduct our DIR-Net on real-world resource-limited devices which achieves 11.1 × storage saving and 5.4 × speedup. [ABSTRACT FROM AUTHOR]

A method for determining the weights of a binary neural network based on its decomposition into elementary modules is presented. The approach allows tuning the weight coefficients of all the network connections at the stage of its designing, which eliminates the implementation of time-consuming iterative algorithms for training the network during its operation. An algorithm and an example of calculating the weights are given. [ABSTRACT FROM AUTHOR]

As the memory footprint requirement and computational scale concerned, the light-weighted Binary Neural Networks (BNNs) have great advantages in limited-resources platforms, such as AIoT (Artificial Intelligence in Internet of Things) edge terminals, wearable and portable devices, etc. However, the binarization process naturally brings considerable information losses and further deteriorates the accuracy. In this article, three aspects are introduced to better the binarized ReActNet accuracy performance with a more low-complex computation. Firstly, an improved Binarized Ghost Module (BGM) for the ReActNet is proposed to increase the feature maps information. At the same time, the computational scale of this structure is still kept at a very low level. Secondly, we propose a new Label-aware Loss Function (LLF) in the penultimate layer as a supervisor which takes the label information into consideration. This auxiliary loss function makes each category’s feature vectors more separate, and improve the final fully-connected layer’s classification accuracy accordingly. Thirdly, the Normalization-based Attention Module (NAM) method is adopted to regulate the activation flow. The module helps to avoid the gradient saturation problem. With these three approaches, our improved binarized network outperforms the other state-of-the-art methods. It can achieve 71.4% Top-1 accuracy on the ImageNet and 86.45% accuracy on the CIFAR-10 respectively. Meanwhile, its computational scale OPs is the least $0.86\times {10}^{8}$ compared with the other mainstream BNN models. The experimental results prove the effectiveness of our proposals, and the study is very helpful and promising for the future low-power hardware implementations.

The outstanding performance of deep convolutional neural networks comes from their effective extraction and learning ability. Although binary neural networks (BNNs) have the obvious advantages of low storage and high efficiency over their full-precision counterparts on resource-constrained hardware devices, the accuracy degradation brought by binary quantization is still an unavoidable problem. The activation distribution in BNNs is a key factor affecting network performance. To elevate the accuracy of BNNs, in this paper, we propose to regulate the activation distribution to strengthen the representation ability of BNNs. We first propose an Information Entropy enhancement Basic block (IEBlock) to build a competitive baseline model with higher information entropy of output activation distribution. Specifically, we build the IEBlock by deliberately reorganizing the position of the elements in the normal basic block based on a deep analysis of the information flow. After that, we propose a Depth-aware Activation Distribution Amendment (DADA) module, which learns the interdependencies of feature channels to amend the activation distribution with information loss after binary convolution. Extensive experiments demonstrate that our method effectively improves the information entropy of binary activations and elevates the accuracy of BNNs. Our method has outperformed the state-of-the-art methods on CIFAR-10 and ImageNet datasets. Code is available at: https://github.com/tomorrow-rain/RAD-BNN • A BNN is implemented considering the information entropy of activations. • Depth-aware channel dependencies are built to regulate the activations. • SOTA results are achieved on CIFAR-10 and ImageNet datasets with the BNNs. [ABSTRACT FROM AUTHOR]

In this paper, we find that the conventional convolution operation becomes the bottleneck for extremely efficient binary neural networks (BNNs). To address this issue, we open up a new direction by introducing a reshaped point-wise convolution (RPC) to replace the conventional one to build BNNs. Specifically, we conduct a point-wise convolution after rearranging the spatial information into depth, with which at least $2.25\times $ computation reduction can be achieved. Such an efficient RPC allows us to explore more powerful representational capacity of BNNs under a given computation complexity budget. Moreover, we propose to use a balanced activation (BA) to adjust the distribution of the scaled activations after binarization, which enables significant performance improvement of BNNs. After integrating RPC and BA, the proposed network, dubbed as RB-Net, strikes a good trade-off between accuracy and efficiency, achieving superior performance with lower computational cost against the state-of-the-art BNN methods. Specifically, our RB-Net achieves 66.8% Top-1 accuracy with ResNet-18 backbone on ImageNet, exceeding the state-of-the-art Real-to-Binary Net (65.4%) by 1.4% while achieving more than $3\times $ reduction (52M vs. 165M) in computational complexity. [ABSTRACT FROM AUTHOR]

Skeleton-based action recognition is an essential yet challenging visual task, whose accuracy has been remarkably improved due to the successful application of graph convolutional networks (GCNs). However, high computation cost and memory usage hinder their deployment on resource-constrained environment. To deal with the issue, in this paper, we introduce two novel progressive binary graph convolutional network for skeleton-based action recognition PB-GCN and PB-GCN * , which can obtain significant speed-up and memory saving. In PB-GCN, the filters are binarized, and in PB-GCN * , both filters and activations are binary. Specifically, we propose a progressive optimization, i.e., employing ternary models as the initialization of binary GCNs (BGCN) to improve the representational capability of binary models. Moreover, the center loss is exploited to improve the training procedure for better performance. Experimental results on two public benchmarks (i.e., Skeleton-Kinetics and NTU RGB + D) demonstrate that the accuracy of the proposed PB-GCN and PB-GCN * are comparable to their full-precision counterparts and outperforms the state-of-the-art methods, such as BWN, XNOR-Net, and Bi-Real Net. [ABSTRACT FROM AUTHOR]

A synaptic cell composed of two tunnel field-effect transistors (TFETs) which is capable of XNOR operation for binary neural networks has been experimentally demonstrated. Our proposed synaptic TFETs feature lower current during inference and higher programming efficiency during weight transfer than conventional synaptic transistors. Moreover, the fabricated synaptic TFET arrays satisfy the neurobiological energy requirement $(\!\sim 10$ fJ per synaptic event) and low bit-error rate of $6.7\times10$ −7%. [ABSTRACT FROM AUTHOR]

Enabling deep learning technology on the mobile web can improve the user’s experience for achieving web artificial intelligence in various fields. However, heavy DNN models and limited computing resources of the mobile web are now unable to support executing computationally intensive DNNs when deploying in a cloud computing platform. With the help of promising edge computing, we propose a lightweight collaborative deep neural network for the mobile web, named LcDNN, which contributes to three aspects: (1) We design a composite collaborative DNN that reduces the model size, accelerates inference, and reduces mobile energy cost by executing a lightweight binary neural network (BNN) branch on the mobile web. (2) We provide a jointly training method for LcDNN and implement an energy-efficient inference library for executing the BNN branch on the mobile web. (3) To further promote the resource utilization of the edge cloud, we develop a DRL-based online scheduling scheme to obtain an optimal allocation for LcDNN. The experimental results show that LcDNN outperforms existing approaches for reducing the model size by about 16x to 29x. It also reduces the end-to-end latency and mobile energy cost with acceptable accuracy and improves the throughput and resource utilization of the edge cloud. [ABSTRACT FROM AUTHOR]

Significant volumes of wastewater are routinely generated during agro-industry processing, amounting to millions of tonnes annually. In line with the circular economy concept, there could be a possibility of simultaneously treating the wastewater and recovering bio-energy resources such as bio-hydrogen. This study aimed to model the effect of different process parameters that could influence wastewater treatment and bio-energy recovery from agro-industrial wastewaters. Three agro-industrial wastewaters from dairy, chicken processing, and palm oil mills were investigated. Eight data-driven machine learning algorithms namely linear support vector machine (LSVM), quadratic support vector machine (QSVM), cubic support vector machine (CSVM), fine Gaussian support vector machine (FGSVM), binary neural network (BNN), rotation quadratic Gaussian process regression (RQGPR), exponential quadratic Gaussian process regression (EQGPR) and exponential Gaussian process regression (EGPR) were employed for the modeling process. The datasets obtained from the three agro-industrial processes were employed to train and test the models. The LSVM, QSVM, and CSVM did not show an impressive performance as indicated by the coefficient of determination (R2) < 0.7 for the prediction of hydrogen produced from wastewaters using the three agro-industrial processes. The LSVM, QSVM, and CSVM models were also characterized by high prediction errors. Superior performance was displayed by FGSVM, BNN, RQGPR, EQGPR, and EQGPR models as indicated by the high R2 > 0.9, an indication of better predictability with minimized prediction errors as indicated by the low root mean square error (RMSE), mean square error (MSE), and mean absolute error (MAE).

End-to-end learning of the communication system regards the transmitter, channel, and receiver as a neural network-based autoencoder. This approach enables joint optimization of both the transmitter and receiver and can learn to communicate more efficiently than model-based ones. Despite the achieved success, high complexity is the major disadvantage that hinders its further development, while low-precision compression such as one-bit quantization is an effective solution. This study proposed an autoencoder communication system composed of binary neural networks (BNNs), which is based on bit operations and has a great potential to be applied to hardware platforms with very limited computing resources such as FPGAs. Several modifications are explored to further improve the performance. Experiments showed that the proposed BNN-based system can achieve a performance similar to that of the existing neural network-based autoencoder systems while largely reducing the storage and computation complexities.

Magnetic RAM (MRAM)-based crossbar array has a great potential as a platform for in-memory binary neural network (BNN) computing. However, the number of word-lines that can be activated simultaneously is limited because of the low $I_{H}/I_{L}$ ratio of MRAM, which makes BNNs more vulnerable to the device variation. To address this issue, we propose an algorithm/hardware co-design methodology. First, we choose a promising memristor crossbar array (MCA) structure based on the sensitivity analysis to process variations. Since the selected MCA structure becomes more tolerant to the device variation when the number of 1 in input activation values decreases, we apply an input distribution regularization scheme to reduce the number of 1 in input of BNNs during training. We further improve the robustness against device variation by adopting the retraining scheme based on knowledge distillation. Experimental results show that the proposed method makes BNNs more tolerant to MRAM variation and increases the number of parallel word-line activation significantly; thereby achieving improved throughput and energy efficiency.

An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>105) with sub-pA off current, and a low programming voltage (< 9 V) is used to achieve a sufficient dynamic range of synaptic weights (>103) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only < 0.5 % degradation of classification accuracy compared to the baseline accuracy, which is suitable to perform off-chip event-driven computation using parallel read-out operations. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) is a promising approach for energy cost reduction due to data movement between memory and processor for running data-intensive deep learning applications on the computing systems. Together with Binary Neural Network (BNN), IMC provides a viable solution for running deep neural networks at the edge devices with stringent memory and energy constraints. In this paper, we propose a novel 10T bit-cell with a back-end-of-line (BEOL) metal-oxide-metal (MOM) capacitor laid on pitch for in-memory computing. Our IMC bit-cell, when arranged in a memory array, performs binary convolution (XNOR followed by Bit-count operations) and binary activation generation operations. We show, when binary layers of BNN are mapped into our IMC arrays for MNIST digit classification, 98.75% accuracy with energy efficiency of 2193 TOPS/W and throughput of 22857 GOPS can be obtained. We determine the memory array size considering the word-line and bit-line nonidealities and show how these impact classification accuracy. We analyze the impact of process variations on classification accuracy and show how word-line pulse tunability provided by our design can be used to improve the robustness of classification under process variations.

Due to the increasing demand of high energy-efficient processor for deep neural networks, traditional neural network engines with high-precision weights and activations that usually occupies huge on/off-chip resources with large power consumption are no longer suitable for Internet-of-Things applications. Binary neural networks (BNNs) reduce memory size and computation complexity, achieving drastically increased energy efficiency. In this brief, an energy-efficient time-domain binary neural network engine is optimized for image recognition, with time-domain accumulation (TD-MAC), timing error detection based adaptive voltage scaling design and the related approximate computing. The proposed key features are: 1) an error-tolerant adaptive voltage scaling system with TD-MAC chain truncation for aggressive power reduction, working from near-threshold to normal voltage; 2) architectural parallelism and data reuse with 100% TD-MAC utilization; 3) low power TD-MAC based on analog delay lines. Fabricated in a 28nm CMOS process, the whole system achieves a maximum 51.5TOPS/W energy efficiency at 0.42V and 25MHz, with 99.6% accuracy on MNIST dataset. When the length of the TD-MAC chain is truncated by configuration, with a 90% accuracy on MNIST and a 150MHz, the proposed BNN achieves a power-saving of 13.2% and a further energy efficiency increasing of 67.6%. [ABSTRACT FROM AUTHOR]

Deep neural networks are widely used in computer vision, pattern recognition, and speech recognition and achieve high accuracy at the cost of remarkable computation. High computational complexity and memory accesses of such networks create a big challenge for using them in resource-limited and low-power embedded systems. Several binary neural networks have been proposed that exploit only 1-bit values for both weights and activations. Binary neural networks substitute complex multiply-accumulation operations with bitwise logic operations to reduce computations and memory usage. However, these quantized neural networks suffer from accuracy loss, especially in big datasets. In this paper, we introduce a quantized neural network with 2-bit weights and activations that is more accurate compared to the state-of-the-art quantized neural networks, and also the accuracy is close to the full precision neural networks. Moreover, we propose E2BNet, an efficient MAC-free hardware architecture that increases power efficiency and throughput/W about 3.6 × and 1.5 × , respectively, compared to the state-of-the-art quantized neural networks. E2BNet processes more than 500 images/s on the ImageNet dataset that not only meet real-time requirements of images/video processing but also can be deployed on high frame rate video applications. [ABSTRACT FROM AUTHOR]

Neural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structural features of a recently proposed memory-based programmable logic device, compare it with the standard structure, and test it on common datasets with full and binary precision, respectively. The experimental results reveal that the new structured network can provide almost consistent full-precision performance and binary-precision performance ranging from 61.0% to 78.8% after using sparser connections and about 50% reduction in the size of the weight matrix. [ABSTRACT FROM AUTHOR]

Binarized convolutional neural network (BCNN) is a promising and efficient technique toward the landscape of Artificial Intelligence of Things (AIoT) applications. In-Memory Computing (IMC) has widely been studied to accelerate the inference task of BCNN to maximize both throughput and energy efficiency. However, existing IMC circuits and architectures are only optimized for a fixed kernel size and nominal voltage operation, which poses practical limitations on optimal network architecture exploration and additional energy efficiency benefits. In this brief, we present a reconfigurable, near-threshold IMC-based BCNN accelerator design. The IMC-based accelerator architecture is scalable for different kernels sizes (3 × 3 × d and 5 × 5 × d) and achieves high resource utilization for both cases. Moreover, the IMC bitcell is optimized for reliable near-threshold operation. Implemented in a 55-nm CMOS process, our proposed reconfigurable IMC-based BCNN accelerator achieves 5526 TOPS/W energy efficiency at 0.4V, which is 6.38 × higher compared to the state-of-the-art designs. The inference accuracies of our proposed design are 97.73%, 82.56%, and 92.61% across three datasets (MNIST, CIFAR-10, and SVHN), respectively. [ABSTRACT FROM AUTHOR]

Ultrafast current-driven domain wall (DW) motions have been realized in ferrimagnetic (FiM) nanowires. However, the FiM dynamics can be significantly affected by the Joule-heating. In this work, we propose a highly efficient XNOR logic gate by properly leveraging the thermal effect on the FiM DW motions. Its functionality and advantageous performance have been confirmed by the micromagnetic simulations. Moreover, majority logic and full adder functions can also be reconfigured based on the proposed scheme. Lastly, a fully FiM DW based binary neural network (BNN) is built, which provides low energy consumption, short delay and excellent accuracy. [ABSTRACT FROM AUTHOR]

You Only Look Once (YOLO), known for its real-time performance and outstanding accuracy, has emerged as a prominent framework for object detection tasks. However, deploying YOLO on resource-constrained edge devices poses challenges due to its substantial memory requirements. In this paper, we propose MPQ-YOLO, an ultra-low mixed-precision quantization framework designed for edge device deployment. The core idea is to integrate 1-bit Backbone quantization and 4-bit Head quantization with dedicated training techniques. Specifically, we analyze the effect of numerical distribution on the performance of binary neural networks (BNNs), and based on this, we design a backbone with only 1-bit convolution. Then, we introduce a trainable scale and Progressive Network Quantization (PNQ) training strategy to bridge the Backbone and Head for end-to-end quantization training. The former is applied to both weights and activations within the 4-bit Head, enabling effective gradient propagation. The latter mitigates oscillation caused by mixed precision training, promoting smoother training and faster model convergence. Extensive experiments on VOC and COCO datasets demonstrate that MPQ-YOLO achieves a good trade-off between model compression and detection performance. Specifically, compared to the full-precision model, MPQ-YOLO achieves compression of up to 16.3 × and 14.2 × in terms of computational complexity and model size, respectively, while maintaining relatively high detection accuracy, i.e., 74.7% on VOC and 51.5% on COCO. To the best of our knowledge, MPQ-YOLO is the first YOLO framework with dual low mixed-precision quantization. Moreover, compared to the existing layer-wise mixed-precision quantization methods which cause redundant data processing and massive data movement, MPQ-YOLO offers a more hardware-designer-friendly and straightforward solution through efficient resource utilization and reuse. [ABSTRACT FROM AUTHOR]

Neuromorphic computing, which mimics the structure and principles of the human brain, has the potential to facilitate the hardware implementation of next-generation artificial intelligence systems and process large amounts of data with very low power consumption. Among them, the XNOR synapse-based Binary Neural Network (BNN) has been attracting attention due to its compact neural network parameter size and low hardware cost. The previous XNOR synapse has drawbacks, such as a trade-off between cell density and accuracy. In this work, we show nonvolatile XNOR synapses with high density and accuracy using a monolithically stacked complementary ferroelectric field-effect transistor (C-FeFET) composed of a p-type Si MFMIS-FeFET at the bottom and a 3D stackable n-type Al:IZTO MFS-FeTFT, achieving 60F 2 per cell (2C-FeFET). For adjusting the threshold voltage and improving the switching speed (100 ns) of n-type ferroelectric TFT, we employed a dual-gate configuration and a unique operation scheme, making it comparable to those of Si-based FeFETs. We performed array-level simulation with a 512 × 512 subarray size and a 3-bit flash ADC, demonstrating that the image recognition accuracies using the MNIST and CIFAR-10 data sets were increased by 3.17 and 14.07%, respectively, in comparison to other nonvolatile XNOR synapses. In addition, we performed system-level analysis on a 512 × 512 XNOR C-FeFET, exhibiting an outstanding throughput of 717.37 GOPS and an energy efficiency of 196.7 TOPS/W. We expect that our approach would contribute to the high-density memory systems, logic-in-memory technology, and hardware implementation of neural networks.

Stereo estimation is essential to many applications such as mobile autonomous robots, most of which ask for real-time response, high energy, and storage efficiency. Deep neural networks (DNNs) have shown to yield significant gains in improving accuracy. However, these DNN-based algorithms are challenging to be deployed on energy and resource-constrained devices due to the high computational complexities of DNNs. In this article, we present StereoEngine, a fully pipelined end-to-end stereo vision accelerator that computes accurate dense depth in a real-time and energy-efficient manner. An efficient stereo algorithm is developed and optimized for a high-quality hardware-friendly implementation, that leverages binary neural network (BNN) to learn discriminative binary descriptors to improve the disparity. The design of StereoEngine is a standalone DNN-based stereo vision system where all processing procedures are implemented on a hardware platform. The effectiveness of StereoEngine is evaluated by comprehensive experiments. Compared with software-based implementations on the high-end and embedded Nvidia GPUs, StereoEngine achieves up to $3\times $ , $13\times $ , and $50\times $ speedups, as well as up to $211\times $ , $58\times $ , and $73\times $ energy efficiency improvement, respectively. Furthermore, StereoEngine achieves leading accuracy when compared to state-of-the-art hardware implementations on the challenging KITTI dataset. [ABSTRACT FROM AUTHOR]

• We propose a new concept of information capacity regularization in deep neural networks. • An information loss penalty for regularization of binary neural networks is developed. • Experiments were conducted with today's best performing techniques. • Information loss penalty boosts the accuracy of existing state-of-the-art binary networks. • We statistically prove the efficiency of the new regularization approach on 4 common datasets. Despite the growing popularity of deep learning technologies, high memory requirements and power consumption are essentially limiting their application in mobile and IoT areas. While binary convolutional networks can alleviate these problems, the limited bitwidth of weights is often leading to significant degradation of prediction accuracy. In this paper, we present a method for training binary networks that maintains a stable predefined level of their information capacity throughout the training process by applying Shannon entropy based penalty to convolutional filters. The results of experiments conducted on the SVHN, CIFAR and ImageNet datasets demonstrate that the proposed approach can statistically significantly improve the accuracy of binary networks. [ABSTRACT FROM AUTHOR]

As is well-known, defects precisely affect the lives and functions of the machines in which they occur, and even cause potentially catastrophic casualties. Therefore, quality assessment before mounting is an indispensable requirement for factories. Apart from the recognition accuracy, current networks suffer from excessive computing complexity, making it of great difficulty to deploy in the manufacturing process. To address these issues, this paper introduces binary networks into the area of surface defect detection for the first time, for the reason that binary networks prohibitively constrain weight and activation to +1 and −1. The proposed Bi-ShuffleNet and U-BiNet utilize binary convolution layers and activations in low bitwidth, in order to reach comparable performances while incurring much less computational cost. Extensive experiments are conducted on real-life NEU and Magnetic Tile datasets, revealing the least OPs required and little accuracy decline. When classifying the defects, Bi-ShuffleNet yields comparable results to counterpart networks, with at least 2× inference complexity reduction. Defect segmentation results indicate similar observations. Some network design rules in defect detection and binary networks are also summarized in this paper.

In this article, we demonstrate an energy efficient convolutional neural network (CNN) engine by performing multiply-and-accumulate (MAC) operations in the time domain. The multi-bit inputs are compactly represented as a single pulse width encoded input. This translates into reduced switching capacitance ($C_{\mathrm{ DYN}}$), compared to baseline digital implementation, and can enable low power neural network computing in an edge device. The time-domain CNN engine employs a novel bi-directional memory delay line (MDL) unit to perform signed accumulation of input and weight products. The proposed MDL design leverages standard digital circuits and does not require any capacitors and complex analog-to-digital converters (ADCs) to realize the convolution operation, thereby enabling easy scaling across the process technology nodes. Four speed-up modes and a configurable MDL length are supported to address throughput versus accuracy trade-off of the time-domain computing approach. Delay calibration units have been accommodated to mitigate the process variation induced delay mismatch among concurrently operating MDL units. The proposed time-domain MDL design implements a LeNet-5 CNN engine in a commercial 40-nm CMOS process achieving an energy efficiency of 12.08 TOPS/W, a throughput of 0.365 GOPS at 537 mV in the 16 $\times $ speed-up mode. 40-nm CMOS test-chip measurements over 100 MNIST images show 97% classification accuracy. Simulation results over the entire 10 000 MNIST validation dataset images taking into account the circuit non-ideal effects of the MDL-based time-domain approach show a classification accuracy of 98.42%. The test-chip is operational down to the near-threshold voltage (up to 375 mV) while maintaining the classification accuracy over 90% in the 1 $\times $ speed-up mode. Furthermore, two methods of scaling MDLs to multi-bit weights are proposed. Simulation results for 1000-class AlexNet over 50 000 ImageNet validation dataset images show classification accuracy loss within 1% when compared with software implementation. The proposed MDL based time-domain approach performing 1-bit/8-bit weight and 8-bit input MAC operations when compared with the corresponding baseline digital implementations shows 2.09 $\times $ −2.32 $\times $ higher energy efficiency and 2.22 $\times $ −3.45 $\times $ smaller area. [ABSTRACT FROM AUTHOR]

Neural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structural features of a recently proposed memory-based programmable logic device, compare it with the standard structure, and test it on common datasets with full and binary precision, respectively. The experimental results reveal that the new structured network can provide almost consistent full-precision performance and binary-precision performance ranging from 61.0% to 78.8% after using sparser connections and about 50% reduction in the size of the weight matrix.

Emerging nonvolatile memories (NVMs), including resistive RAM (RRAM), phase-change memory (PCM), and magnetic RAM (MRAM), have opened up new pathways for Computing-In-Memory (CIM). Those NVM technologies can achieve energy-efficient computational operations with only minor modification of the peripheral circuits. Despite many advantages provided by computational NVMs, parallelism is not sufficiently explored in such CIM designs. To break through this limitation on performance gain, we propose a data-streaming design for the NVM-based CIM (e.g., DASM) by leveraging the underlying parallelism in the hardware. DASM benefits from the massive parallelism of data-streaming computing, reduction in data movement of the CIM, and the nonvolatility of memory arrays. Specifically, data streaming operations can be implemented with CIM bitwise operations in both read-out and write-in procedures. In addition, we use the multilevel power gating for the memory array and connections to further boost the performance. Finally, we study a case of inference process for the quantized deep-neural-network-based on the DASM design. DASM architecture achieves $47.8\times $ , $5.1\times $ , $2.1\times $ speedup compared to the NVIDIA Jetson TK1 embedded GPU board, Intel Xeon E5-2640 CPU, the state-of-the-art field-programmable gate array (FPGA) design, with much lower power consumption. [ABSTRACT FROM AUTHOR]

A reconfigurable field-effect transistor (RFET) with memory functionality is proposed as a new high-density synaptic device capable of exclusive NOR (XNOR) operation for a binary neural network (BNN). A RFET with three gates is used in this letter, consisting of two program gates (PGs) electrically connected to each other and a control gate (CG) between the PGs. By changing the polarity of the PG bias or the polarity of the charge trapped in Si3N4 layer on the PGs, the RFET operates as an ${n}$ - or a ${p}$ -MOSFET having a CG as a switching gate. The XNOR operation is successfully demonstrated in a fabricated RFET. The on/off current ratio (the ratio of 1 to 0 in the result of the XNOR operation) is ~104 and the current is ~1 nA/ $\mu \text{m}$. Using a RFET as a synaptic device for a BNN is efficient in terms of the area (~8F2/synapse) because XNOR operation can be performed using only one RFET. [ABSTRACT FROM AUTHOR]

With the advent of the Internet of Everything, more and more devices are connected to the Internet every year. In major cities, in order to maintain normal social order, the demand for deployed cameras is also increasing. In terms of public safety, person Re-Identification (ReID) can play a big role. However, the current methods of ReID are to transfer the collected pedestrian images to the cloud for processing, which will bring huge communication costs. In order to solve this problem, we combine the recently emerging edge computing and use the edge to combine the end devices and the cloud to implement our proposed binarized segmented ResNet. Our method is mainly to divide a complete ResNet into three parts, corresponding to the end devices, the edge, and the cloud. After joint training, the corresponding segmented sub-network is deployed to the corresponding side, and inference is performed to realize ReID. In our experiments, we compared some traditional ReID methods in terms of accuracy and communication overhead. It can be found that our method can greatly reduce the communication cost on the basis of basically not reducing the recognition accuracy of ReID. In general, the communication cost can be reduced by four to eight times.

• We provide a new insight on the reason of BNNs' performance degradation. • A novel DBNN model is proposed to handle the accuracy drop of BNNs. • A sparsity-binarization scheme for weight is given to avoid mandatory representation. • A stable binarization strategy for activation is developed with layer normalization. • A customized proximal gradient method is designed to derive diluted binary weights. Binary neural networks (BNNs) are promising on resource-constrained devices because they reduce memory consumption and accelerate inference effectively. However, they are still potential on performance improvement. Prior studies attribute performance degradation of BNNs to limited representation ability and gradient mismatch. In this paper, we find that it also results from the mandatory representation of small full-precision auxiliary weights to large values. To tackle with this issue, we propose an approach dubbed as Diluted Binary Neural Network (DBNN). Besides avoiding mandatory representation effectively, the proposed DBNN also alleviates sign flip problem to a large extent. For activations, we jointly minimize quantization error and maximize information entropy to develop the binarization scheme. Compared with existing sparsity-binarization approaches, DBNN trains network from scratch without other procedures and achieves larger sparsity. Experiments on several datasets with various networks demonstrate the superiority of our approach. [ABSTRACT FROM AUTHOR]

• M -ary quantized neural network is proposed with adjustable M to balance between end performance and implementation cost. • Bayesian quantization is implemented to assure robustness in quantization learning. • A new multi-spike-and-slab prior is discovered to represent asymmetric parameters in Bayesian quantization. • Joint training of neural networks for compression and classification is developed. • State-of-the-art performance is achieved for image recognition in various competing tasks. This paper develops a robust model compression for neural networks via parameter quantization. Traditionally, quantized neural networks (QNN) were constructed by binary or ternary weights where the weights were deterministic. This paper generalizes QNN in two directions. First, M -ary QNN is developed to adjust the balance between memory storage and model capacity. The representation values and the quantization partitions in M -ary quantization are mutually estimated to enhance the resolution of gradients in neural network training. A flexible quantization with asymmetric partitions is formulated. Second, the variational inference is incorporated to implement the Bayesian asymmetric QNN. The uncertainty of weights is faithfully represented to enhance the robustness of the trained model in presence of heterogeneous data. Importantly, the multiple spike-and-slab prior is proposed to represent the quantization levels in Bayesian asymmetric learning. M -ary quantization is then optimized by maximizing the evidence lower bound of classification network. An adaptive parameter space is built to implement Bayesian quantization and neural representation. The experiments on various image recognition tasks show that M -ary QNN achieves similar performance as the full-precision neural network (FPNN), but the memory cost and the test time are significantly reduced relative to FPNN. The merit of Bayesian M -ary QNN using multiple spike-and-slab prior is investigated. [ABSTRACT FROM AUTHOR]