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The ultra-high frequency (UHF) tag IC’s main part of the power management unit (PMU) design technique is presented. The technique is a step-by-step algorithm for designing a PMU and consists of five interrelated stages. At the first stage, the requirements for the parameters of the PMU (output voltage, output DC power, efficiency, output capacitor capacity) and the Q-factor of the tag analog front-end are determinates. At the second stage, the design of an electrical circuit of a voltage multiplier (VM) is carried out. VM is required to convert the voltage of the input radio frequency (RF) signal into an DC voltage. During the third stage, the design of the electrical circuit of the DC voltage limiter is carried out, which is necessary to reduce the output voltage of VM to a safe level. The result of stage 4 is an electrical circuit of surge protection designed to provide the required level of immunity of the tag IC to the effects of electrostatic discharge and a high-power RF signal. As part of the final stage, the evaluation and alignment with the required Q-factor value of the tag IC analog front-end is carried out. The proposed technique can be used for the development of domestic UHF tag ICs (ISO 18000-6C, GJB 7377.1, etc.) based on CMOS technological processes, including ICs designed for radio frequency identification of critical infrastructure objects. Using the presented technique, the design of a PMU with an estimated efficiency value of 70%, an estimated Q-factor of the analog front-end of less than 15 at an RF input signal power of -12.7 dBm was performed.

Results of designing the low-noise amplifier, quadrature demodulator, and baseband amplifier with an integrated low-pass filter for the UHF radio frequency identification receiver are presented. IP-blocks are designed for implementation in the domestic CMOS 180 nm technology process. The low-noise amplifier is implemented with integrated single pole double throw switches based on the MOSFETs which are needed for bypass mode realization at the RF input. The benefits of this approach are increased input linearity of the receiver by no less than 30 dB with an increase of a noise figure. The quadrature demodulator is realized according to a typical design based on the passive MOSFET mixer core. The programmable-gain baseband amplifier is implemented with an integrated low-pass filter based on Tow-Thomas biquad architecture. IP-blocks designed for use in an RFID reader transceiver VLSI IC with sensitivity value no more than -75 dBm and input linearity value not less than 10 dBm in a «Talk» mode. The trustiness of the receiver is provided by the full-cycle design procedure and verification under experimental investigation. The electric parameters values of the proposed receiver correspond to foreign VLSIs implemented in a CMOS process with the same technology nodes. Thus, it is important to design the domestic ISO 18000-6C reader equipment intended for critical infrastructure.

Results of designing the specialized RF elements library intended for use in the CMOS 180 nm process are presented. The RF library includes a set of RF MOSFETs for amplifiers and switches design, three types of varactors based on the MOS-structure, spiral inductors, MIM-capacitors and other elements. The RF library is intended for use in combination with CAD Cadence Virtuoso IC and is focused on designing a set of amplifiers, frequency oscillators and convertors, controlled attenuators and phase shifters microwave IP-blocks of the transceiver VLSI. A test chip is developed with using the presented RF library, focused on conducting research by probe methods and containing 13 types of basic elements and specialized structures for the RF characterization of the domestic CMOS 180 nm process.