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The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS technology, single-event multi-node upsets (MNU) induced by charge sharing has continued to occur in latches when hit by high-energy particles. This paper presents a quadruple-node upset (QNU) tolerant latch design (referred to as P-DICE latch) to achieve both high reliability and low area overhead. The P-DICE latch takes advantage of the error-blocking properties of Cross-Coupled Element and C Element to tolerate QNU, and achieves 100% self-recovery of SNU and DNU. Compared with previous eight MNU hardened latches, the P-DICE latch has the lowest overhead in terms of area, area-power-delay product (APDP), and area-power-delay soft error rate ratio product (APDSP), and has the highest critical charge. Moreover, the proposed P-DICE latch can tolerate QNU caused by high-energy particles to ensure the reliability of the circuit. Compared with eight MNU hardened latches, the proposed P-DICE latch achieves 24.58% reduction in area, 33.05% reduction in power, 17.19% reduction in delay, 48.29% reduction in area-power-delay product, 61.60% reduction in APDSP, and 142.82% improvement in critical charge on average. [ABSTRACT FROM AUTHOR]

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations. [ABSTRACT FROM AUTHOR]