Search

Gallium Phosphide (GaP) has recently received considerable attention as a suitable material for building photonic integrated circuits due to its remarkable optical and piezoelectric properties. Usually, GaP is grown epitaxially on III–V substrates to keep its crystallinity and later transferred to silicon wafers for further processing. Here, an alternative promising route for the fabrication of optomechanical (OM) cavities on GaP epitaxially grown on nominally (001)‐oriented Si is introduced by using a two‐step process consisting of a low‐temperature etching of GaP followed by selective etching of the underneath silicon. The low‐temperature (–30 °C) during the dry‐etching of GaP hinders the lateral etching rate, preserving the pattern with a deviation between the design and the pattern in the GaP layer lower than 5%, avoiding the complex process of transferring and bonding a GaP wafer to a silicon‐on‐insulator wafer. To demonstrate the quality and feasibility of the proposed fabrication route, suspended OM cavities are fabricated and experimentally characterized. The cavities exhibit optical quality factors between 103 and 104 at telecom wavelengths, and localized mechanical resonances ≈3.1 GHz with quality factors ≈63 when measured at room temperature. These results suggest a simple and low‐cost way to build GaP‐based photonic devices directly integrated on industry‐standard Si(001) photonic wafers. [ABSTRACT FROM AUTHOR]

An integrated optical isolator is a crucial part of photonic integrated circuits (PICs). Existing optical isolators, predominantly based on the silicon-on-insulator (SOI) platform, face challenges in integrating with active devices. We propose a broadband, compact TM mode Mach–Zehnder optical isolator based on InP-on-insulator platforms. We designed two distinct magneto-optical waveguide structures, employing different methods for bonding Ce:YIG and InP, namely O2 plasma surface activation direct wafer bonding and DVS-benzocyclobutene (BCB) adhesive bonding. Detailed calculations and optimizations were conducted to enhance their non-reciprocal phase shift (NRPS). At a wavelength of 1550 nm, the direct-bonded waveguide structure achieved a 30 dB bandwidth of 72 nm with a length difference of 0.256 µm. The effects of waveguide arm length, fabrication accuracy, and dimensional errors on the device performance are discussed. Additionally, manufacturing tolerances for three types of lithographic processes were calculated, serving as references for practical manufacturing purposes. [ABSTRACT FROM AUTHOR]

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

The availability of thin-film lithium niobate on insulator (LNOI) and advances in processing have led to the emergence of fully integrated LiNbO3 electro-optic devices. Yet to date, LiNbO3 photonic integrated circuits have mostly been fabricated using non-standard etching techniques and partially etched waveguides, that lack the reproducibility achieved in silicon photonics. Widespread application of thin-film LiNbO3 requires a reliable solution with precise lithographic control. Here we demonstrate a heterogeneously integrated LiNbO3 photonic platform employing wafer-scale bonding of thin-film LiNbO3 to silicon nitride (Si3N4) photonic integrated circuits. The platform maintains the low propagation loss (<0.1 dB/cm) and efficient fiber-to-chip coupling (<2.5 dB per facet) of the Si3N4 waveguides and provides a link between passive Si3N4 circuits and electro-optic components with adiabatic mode converters experiencing insertion losses below 0.1 dB. Using this approach we demonstrate several key applications, thus providing a scalable, foundry-ready solution to complex LiNbO3 integrated photonic circuits. Lithium niobate plays an important role in integrated photonics, but its widespread application requires a reliable solution. Here, the authors present a wafer-scale approach to LNOI integration via wafer bonding to silicon nitride PICs. [ABSTRACT FROM AUTHOR]

In this letter, we present a photoreceiver front-end circuit that consists of an InP p-i-n photodetector (PIN PD) on an InP transimpedance amplifier (TIA) with double HBTs (DHBTs), in which the key integrated fabrication route of a transfer-printing (TP) process is introduced. Prior to integration, PDs and TIAs are individually fabricated on their respective wafers. Then, a discrete PD with only active layers is transferred onto the destination on a TIA wafer, thereafter, an on-chip coplanar waveguide connection is integrated. The PIN PD and DHBT TIA exhibit excellent performance, characterized by a responsivity of 0.51 A/W at $1.55~\mu \text{m}$ with a bandwidth of 20 GHz and a transimpedance gain of 36 dB $\Omega $ with a bandwidth of 27 GHz, respectively. Finally, the monolithically integrated circuit demonstrates a better frequency response by maximally reducing the parasitic effect, with an open clear eye diagram under a 20 Gb/s nonreturn-to-zero pattern, which evidently manifests its ability for ultrahigh-rate data operation. The present work, by employing a TP process, overcomes the issues in integrating discrete optoelectronic devices and proposes a unique approach for monolithic optoelectronic integrated circuit fabrication. [ABSTRACT FROM AUTHOR]

We employed creatively cold isostatic pressing technology to develop room-temperature bonding of Si–Si using 200-nm Au layers, which the ultra-high pressure was transmitted equally to Si–Si bonding samples by direct contact with the pressure medium during the cold isostatic pressing. We explored the influence of bonding pressure on the bonding rate. It was found that ultra-dense interconnects can be realized and the bonding rate increased with the increase of bonding pressure, which was attributed to the increased metal bond density. With the help of an excellent plastic deformation capacity of Au layers and ultra-high uniform isostatic pressing technology, a bonding rate of the whole 2-in. wafer reached 96.37% observed by scanning acoustic microscope. Simultaneously, in accord with the experiment results, we proposed the bonding mechanism model and discussed it in detail. Furthermore, taking laser lift-off as the front-end process, GaN HEMT devices were successfully transferred from sapphire to Si substrates with this method. Bonded GaN devices on Si substrate have been characterized. The dc characteristics showed an increase in the electrical performance of the GaN HEMT with maximum current density changing from 254 to 290 mA/mm. With the advantages of room-temperature bonding and without surface treatment, the technique was available in high-quality integration of chips. This room-temperature bonding via an ultra-high isostatic pressing strategy may inspire the development of a heterogeneous interconnection architecture and functional integrated circuits delivering a monolithic-like performance in the future hyper-scaling era. [ABSTRACT FROM AUTHOR]

Featured Application: Compact lasers integrated onto SOI for optical communications. The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity and scalability. However, Si itself cannot provide an efficient emitting light source due to its indirect bandgap. Therefore, the integration of III-V semiconductors on Si wafers allows us to benefit from the III-V emitting properties combined with benefits offered by the Si photonics platform. Direct epitaxy of InP-based materials on 300 mm Si wafers is the most promising approach to reduce the costs. However, the differences between InP and Si in terms of lattice mismatch, thermal coefficients and polarity inducing defects are challenging issues to overcome. III-V/Si hetero-integration platform by wafer-bonding is the most mature integration scheme. However, no additional epitaxial regrowth steps are implemented after the bonding step. Considering the much larger epitaxial toolkit available in the conventional monolithic InP platform, where several epitaxial steps are often implemented, this represents a significant limitation. In this paper, we review an advanced integration scheme of AlGaInAs-based laser sources on Si wafers by bonding a thin InP seed on which further regrowth steps are implemented. A 3 µm-thick AlGaInAs-based MutiQuantum Wells (MQW) laser structure was grown onto on InP-SiO2/Si (InPoSi) wafer and compared to the same structure grown on InP wafer as a reference. The 400 ppm thermal strain on the structure grown on InPoSi, induced by the difference of coefficient of thermal expansion between InP and Si, was assessed at growth temperature. We also showed that this structure demonstrates laser performance similar to the ones obtained for the same structure grown on InP. Therefore, no material degradation was observed in spite of the thermal strain. Then, we developed the Selective Area Growth (SAG) technique to grow multi-wavelength laser sources from a single growth step on InPoSi. A 155 nm-wide spectral range from 1515 nm to 1670 nm was achieved. Furthermore, an AlGaInAs MQW-based laser source was successfully grown on InP-SOI wafers and efficiently coupled to Si-photonic DBR cavities. Altogether, the regrowth on InP-SOI wafers holds great promises to combine the best from the III-V monolithic platform combined with the possibilities offered by the Si photonics circuitry via efficient light-coupling. [ABSTRACT FROM AUTHOR]

III–V materials, such as InGaAs and InP, are highly attractive for high-performance electronics and optoelectronics owning to their high carrier mobilities and potential for bandgap engineering. Integration on silicon substrates, however, is a key requirement to enable widespread adoption of these materials. In this work, direct wafer bonding (DWB) of III–V materials is explored as a low-temperature enabling technology for Si integration. For high-performance logic and RF electronics, DWB is compared to competing integration technologies and is shown to exhibit higher device performance due to its relatively low process complexity and thermal impact (~300 °C). Due to the low thermal impact of DWB, it is also uniquely suitable for 3-D integration, i.e., vertical stacking of multiple functional layers. III–V optoelectronics are attractive in such 3-D stacks, where they can enable high-efficiency tunable lasers together with Si photonics integrated circuits. DWB is here compared to selective epitaxy as an integration route for InP-on-Si microdisk lasers. Plasmonics are explored as well, allowing scaling of integrated III–V photonic devices beyond the diffraction limit of light. The results of this work show that DWB is a highly promising integration route for III–V materials for both electronics and optoelectronics applications. [ABSTRACT FROM AUTHOR]

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal–silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion. [ABSTRACT FROM AUTHOR]

A heterogeneously integrated InGaN laser diode (LD) on Si is proposed as a path toward visible wavelength photonic integrated circuits (PICs) on Si. Herein, InGaN films are vertically stacked on a TiO2 waveguide (WG) fabricated on a Si wafer by bonding. In the light propagation direction, it is composed of a hybrid InGaN/TiO2 section, a TiO2 WG, an adiabatic taper, and mirrors that can form a cavity. As the refractive index of GaN is well matched with that of TiO2, the optical transverse mode extends to both the GaN and TiO2 in a hybrid mode. Modes between a hybrid InGaN/TiO2 and a pure TiO2 WG can transfer with an adiabatic taper structure. The coupling loss is calculated to be less than 0.5 dB with fairly short taper length of 78 μm and tip width of 200 nm. GaN substrate removal and bonding are critical fabrication steps of this LD and PIC. The substrate removal is successfully done by photoelectrochemical etching. Although direct bonding of GaN wafers with thermal oxide on Si is successful, GaN epitaxial wafers are more difficult. An implication and remedy of this is discussed in terms of surface roughness of GaN epitaxial film. [ABSTRACT FROM AUTHOR]

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance. [ABSTRACT FROM AUTHOR]

A method to passively align bonded components without direct mechanical contact has been developed. This method uses the pressure field generated by the squeeze flow between the parts during the bonding process to increase the parallelism of planar components. A computational fluid dynamic (CFD) model has been developed to study the squeeze flow phenomenon and to determine generated efforts. Based on these calculations, an assembly stage standing on a flexure pinned linkage has been developed. This assembly stage had two purposes. The first was to show the possibility of passive mechanical alignment using a squeeze flow. The second was to measure efforts to confirm the CFD model. These measurements have led to a refined CFD model taking into account the non-Newtonian behavior of the fluid at high shear rates. This technique was initially developed for the assembly of a fiber-optic-to-silicon-chip-interface. Other potential applications could be wafer bonding, bonding of multiple wafer stacks, or 3D integrated circuits. [ABSTRACT FROM AUTHOR]

High-gain millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a planar metamorphic 20-nm gate length InGaAs metal–oxide–semiconductor high-electron-mobility transistor (MOSHEMT) technology on Si. Therefore, an Al2O3/HfO2 layer stack was deposited as a gate dielectric directly on top of an In0.8Ga0.2As channel by atomic layer deposition. The III–V heterostructure was epitaxial grown on a GaAs wafer and subsequently direct wafer bonded to a Si substrate, leading to a high-quality III–V channel formation on Si. The gate layout was optimized for millimeter-wave and submillimeter-wave integrated circuit applications using T-gates and wet chemical recess etching to minimize the parasitic gate capacitances. For a $2 \times 10 \,\,\mu \text{m}$ gate width transistor, a transit frequency $\text{f}_{\textrm {T}}$ of 200 GHz and a record maximum oscillation frequency $\text{f}_{\textrm {max}}$ of 640 GHz were extrapolated. A realized three-stage cascode amplifier circuit demonstrated a maximum gain of 21 dB at 278 GHz and a small-signal gain of more than 17 dB between 222 and 284 GHz. The total chip size of the millimeter-wave amplifier MMIC was only $0.5\,\,\times \,\,1.2$ mm2. To verify the RF performance of the III–V MOSHEMT on Si technology, all devices and circuits have been reproduced using an InGaAs MOSHEMT on GaAs technology, which has been processed simultaneously within the same wafer batch and achieved almost identical results. [ABSTRACT FROM AUTHOR]

In this paper, a high-thermoresistant temporary bonding/debonding system using spin-on glass (SOG) and hydrogenated amorphous silicon layers is proposed for the multichip-to-wafer (MCtW) 3-D integration based on a via-last/backside-via through-silicon via (TSV) approach. The shear strengths of chips bonded to wafers through the SOG layers are evaluated. In addition, the debonding performance of the chips from the wafers is investigated by using the KrF excimer laser irradiation. Finally, a via-last/backside-via MCtW 3-D integration process using the temporary bonding/debonding system is demonstrated to show the high feasibility with the successful interconnect formation of a Cu-TSVs daisy chain (10 $\mu \text{m}$ in diameter and 50 $\mu \text{m}$ in depth) with a SiO2 liner dielectric deposited by O3-tetraethylorthosilicate chemical vapor deposition at 350 °C. [ABSTRACT FROM AUTHOR]

In this paper, the low temperature direct wafer-bonding technique under 350 °C is used to fabricate the capacitive micromachined ultrasonic transducers (CMUTs) and the first illustration of CMUTs with a 15 × 15 array is obtained. In comparison with other wafer-bonding technology under high temperature beyond 400 °C, the thermal stress and thermal deformation of CMUTs produced in the wafer-bonding process can be decreased largely because of low bonding temperature. What's more, the low temperature direct wafer-bonding technique is beneficial to combine the CMUTs chip with integrated circuits (ICs) as well as reduce the parasitic capacitance. Based on the low temperature direct wafer-bonding process, a silicon-on-insulator (SOI) wafer with the silicon device layer used for transducer membrane and a low-resistivity silicon substrate with the structured SiO 2 layer are bonded to fabricate the main structure of CMUTs. Therefore, the parasitic capacitance of CMUTs can be further reduced since there is no metal auxiliary layer existing during the bonding process. The structure morphology and electrical characterization of fabricated CMUTs are tested in this paper. Then, the impedance-frequency curve and the corresponding phase-frequency curve of the CMUTs are obtained perfectly, which demonstrate that the fabricated CMUTs based on the low-temperature direct wafer-bonding technique present the fine mechanical and electrical characteristics. [ABSTRACT FROM AUTHOR]

We report the current status of the development of our new detectors for far-infrared (FIR) astronomy. We develop Blocked-Impurity-Band (BIB)-type Ge detectors to realize large-format compact arrays covering a wide FIR wavelength range up to 200 $$\upmu $$ m. We fabricated Ge junction devices of different physical parameters with a BIB-type structure, using the room temperature, surface-activated wafer bonding (SAB) method. We measured the absolute responsivity and the spectral response curve of each device at low temperatures, using an internal blackbody source in a cryostat and a Fourier transform spectrometer, respectively. The results show that the SAB Ge junction devices have significantly higher absolute responsivities and longer cut-off wavelengths of the spectral response than the conventional bulk Ge:Ga device. Based upon the results, we discuss the optimum parameters of SAB Ge junction devices for FIR detectors. We conclude that SAB Ge junction devices possess a promising applicability to next-generation FIR detectors covering wavelengths up to $$\sim $$ 200 $$\upmu $$ m with high responsivity. As a next step, we plan to fabricate a BIB-type Ge array device in combination with a low-power cryogenic readout integrated circuit. [ABSTRACT FROM AUTHOR]

Metal wafer bonding is a well-established technology in the semiconductor industry. This technology gains more and more importance due to increasing market demands, particularly for three-dimensional integrated circuits and integration of complementary metal oxide semiconductor and microelectromechanical systems devices used in consumer electronics. Cu-Cu wafer bonding at low temperature is a very attractive process which can be used for both mechanical joints and electrical interconnects in wafer-level processes. In order to facilitate a permanent Cu-Cu bond at low temperature-in contrast to a typical ~400 °C Cu-Cu bonding temperature-the effect of material properties and bonding parameters has to be understood well. Therefore a comprehensive characterization including both, namely surface and interface analysis before and after wafer bonding of non-patterned Cu layers, respectively, is required in order to optimize the Cu-Cu metal wafer bonding process. Low temperature Cu-Cu bonding, namely ≤200 °C, of ~500 nm sputter-deposited Cu films was demonstrated and characterized. Selected analytical methods, such as transmission electron microscopy, Auger electron spectroscopy and electron backscatter diffraction, and their corresponding specimen preparation techniques for microstructure and elemental composition evaluation are introduced. Experimental results of surfaces and interfaces investigation (materials properties with high impact on their bonding behavior), such as the (i) surface roughness, (ii) Cu native oxide, (iii) Cu (surface) purity and (iv) Cu grain size, as well as the influence of the (vi) bonding temperature are presented. [ABSTRACT FROM AUTHOR]

Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO 2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. [ABSTRACT FROM AUTHOR]

The article discusses the potential of the wafer bonding technology for the achievement of improved accuracy for bond alignment. Topics include the increase chip performance offered by three-dimensional integrated circuit (3D-IC), the establishment of some 3D-IC in the middle of the fabrication process, and the transformation of the bonding materials to achieve the successful fusion bonding.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 \mum when 3\,\times\,3-, 5\,\times\,5-, 4\,\times\,9,- or 10\,\times\,10-mm^2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-\mum-pitch Cu–SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu–SnAg microbumps exhibited ohmic contacts, and the resistance of \sim40~m\Omega/bump was sufficiently low for 3-D large-scale integration application. [ABSTRACT FROM AUTHOR]

A new concept of semiconductor wafer bonding, mediated by optical wavelength conversion materials, is proposed and demonstrated. The fabrication scheme provides simultaneous bond formation and interfacial function generation, leading to efficient device production. Wavelength-converting functionalized semiconductor interfacial engineering is realized by utilizing an adhesive viscous organic matrix with embedded fluorescent particles. The bonding is carried out in ambient air at room temperature and therefore provides a cost advantage with regard to device manufacturing. Distinct wavelength conversion, from ultraviolet into visible, and high mechanical stabilities and electrical conductivities in the bonded interfaces are verified, demonstrating their versatility for practical applications. This bonding and interfacial scheme can improve the performance and structural flexibility of optoelectronic devices, such as solar cells, by allowing the spectral light incidence suitable for each photovoltaic material, and photonic integrated circuits, by delivering the respective preferred frequencies to the optical amplifier, modulator, waveguide, and detector materials. [ABSTRACT FROM AUTHOR]

We demonstrate an optically pumped hybrid III-V/Si distributed feedback laser with a small footprint, using sidewall modulated Bragg gratings for optical feedback. Our approach provides high overlap between lasing mode and gain medium and may enable hybrid lasers with improved efficiency, reduced threshold, and minimal size. We fabricate the structure using plasma-assisted wafer bonding, followed by self-aligned lithography and etching. The latter allows us to avoid alignment errors. This approach is a promising avenue toward ultracompact, energy efficient, and scalable monolithically integrated photonic circuits. [ABSTRACT FROM AUTHOR]