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III–V materials, such as InGaAs and InP, are highly attractive for high-performance electronics and optoelectronics owning to their high carrier mobilities and potential for bandgap engineering. Integration on silicon substrates, however, is a key requirement to enable widespread adoption of these materials. In this work, direct wafer bonding (DWB) of III–V materials is explored as a low-temperature enabling technology for Si integration. For high-performance logic and RF electronics, DWB is compared to competing integration technologies and is shown to exhibit higher device performance due to its relatively low process complexity and thermal impact (~300 °C). Due to the low thermal impact of DWB, it is also uniquely suitable for 3-D integration, i.e., vertical stacking of multiple functional layers. III–V optoelectronics are attractive in such 3-D stacks, where they can enable high-efficiency tunable lasers together with Si photonics integrated circuits. DWB is here compared to selective epitaxy as an integration route for InP-on-Si microdisk lasers. Plasmonics are explored as well, allowing scaling of integrated III–V photonic devices beyond the diffraction limit of light. The results of this work show that DWB is a highly promising integration route for III–V materials for both electronics and optoelectronics applications. [ABSTRACT FROM AUTHOR]

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance. [ABSTRACT FROM AUTHOR]

High-gain millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a planar metamorphic 20-nm gate length InGaAs metal–oxide–semiconductor high-electron-mobility transistor (MOSHEMT) technology on Si. Therefore, an Al2O3/HfO2 layer stack was deposited as a gate dielectric directly on top of an In0.8Ga0.2As channel by atomic layer deposition. The III–V heterostructure was epitaxial grown on a GaAs wafer and subsequently direct wafer bonded to a Si substrate, leading to a high-quality III–V channel formation on Si. The gate layout was optimized for millimeter-wave and submillimeter-wave integrated circuit applications using T-gates and wet chemical recess etching to minimize the parasitic gate capacitances. For a $2 \times 10 \,\,\mu \text{m}$ gate width transistor, a transit frequency $\text{f}_{\textrm {T}}$ of 200 GHz and a record maximum oscillation frequency $\text{f}_{\textrm {max}}$ of 640 GHz were extrapolated. A realized three-stage cascode amplifier circuit demonstrated a maximum gain of 21 dB at 278 GHz and a small-signal gain of more than 17 dB between 222 and 284 GHz. The total chip size of the millimeter-wave amplifier MMIC was only $0.5\,\,\times \,\,1.2$ mm2. To verify the RF performance of the III–V MOSHEMT on Si technology, all devices and circuits have been reproduced using an InGaAs MOSHEMT on GaAs technology, which has been processed simultaneously within the same wafer batch and achieved almost identical results. [ABSTRACT FROM AUTHOR]

In this paper, a high-thermoresistant temporary bonding/debonding system using spin-on glass (SOG) and hydrogenated amorphous silicon layers is proposed for the multichip-to-wafer (MCtW) 3-D integration based on a via-last/backside-via through-silicon via (TSV) approach. The shear strengths of chips bonded to wafers through the SOG layers are evaluated. In addition, the debonding performance of the chips from the wafers is investigated by using the KrF excimer laser irradiation. Finally, a via-last/backside-via MCtW 3-D integration process using the temporary bonding/debonding system is demonstrated to show the high feasibility with the successful interconnect formation of a Cu-TSVs daisy chain (10 $\mu \text{m}$ in diameter and 50 $\mu \text{m}$ in depth) with a SiO2 liner dielectric deposited by O3-tetraethylorthosilicate chemical vapor deposition at 350 °C. [ABSTRACT FROM AUTHOR]