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As networks expand in area and scale, there arise needs for high-speed, optimal path-design algorithms that can take into account a number of factors. This paper proposes an optimal path-design algorithm using a neural network. The proposed algorithm can be implemented by hardware digital logic circuits, and enables optimal path design to be performed 104 to 106 times faster than the conventional polynomial-time algorithms. The proposed method is also easily implemented in LSI. Another feature of the proposed method is the use of directed and weighted synaptic connections. © 1998 Scripta Technica, Electron Comm Jpn Pt 1, 81(11): 67–76, 1998 [ABSTRACT FROM AUTHOR]