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We propose a general method to characterize and synthesize correctness-preserving asynchronous wrappers for synchronous processes on a globally asynchronous locally synchronous (GALS) architecture. While a synchronous process may rely on the absence of a signal to trigger a reaction, sensing absence in an asynchronous environment may be unfeasible due to uncontrolled communication latencies. A simple and common solution is to systematically encode and send absence notifications, but it is unduly expensive at run-time. Instead, our approach is based on the theory of weakly endochronous systems, which defines the largest sub-class of synchronous systems where (possibly concurrent) asynchronous evaluation is faithful to the original (synchronous) specification. Our method considers synchronous processes or modules that are specified by synchronization constraints expressed in a high-level multi-clock synchronous reactive formalism. The algorithm uses a compact representation of the abstract synchronization configurations of the analyzed process and determines a minimal set of synchronization patterns generating by union all its possible reactions. A specification is weakly endochronous if and only if these generators do not need explicit absence information. In this case, the set of generators can directly be used to synthesize the concurrent asynchronous multi-rate wrapper of the process. [ABSTRACT FROM AUTHOR]

The domain of Real-Time Embedded (RTE) systems was ackowledged as being largely influential on many feature additions to the recent UML2.0 standard [Björkander, M., FDL'03 Keynote address, 2003]. Work on UML1.4 Scheduling, Performance & Time (SPT) profile also goes in that direction. Still, the paradigms underlying these modeling efforts are that of software components, running on a real-time OSs with physical time constraints and middleware (e.g., RT-Corba) concerns. In other areas of Embedded System Design other paradigms are at work, owing to codesign techniques at the border between software and hardware, or discrete time mathematical engineering (MATLAB/Simulink) and digital signal processing algorithms, etc. The paradigm of Synchronous Reactive (S/R) systems [Benveniste, A., Berry, G.: The synchronous approach to reactive and real-time systems. Proc. IEEE 79(9), 1270–1282 (1991); Benveniste, A., Caspi, P., Edwards, S., Halbwachs, N., Guernic, P.L., de Simone, R.: Synchronous languages twelve years later. Proc. IEEE 91(1), 64–83 (2003)], with discrete logical time and behavior decomposition into instantaneous reactions, proved quite natural in such areas to model mixed hardware/software System-Level Design (SLD). We describe here some of the modeling paradigms needed for a true S/R model framework, and corresponding diagrammatic interpretations. The synchronous reactive domain described here should be dealt with and included in the forthcoming UML profile for “Modeling and Analysis of Real-Time and Embedded systems” (MARTE), whose request for proposal was recently voted at OMG. [ABSTRACT FROM AUTHOR]